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1201 SoCs

1
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3- 2008 standard. The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a...

2
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...

3
10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
Configurable MAC solutions for speeds from 10Gbps to 10Mbps

4
128-bit vector word length ARC VPX2 DSP IP
DesignWare® ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on devices to automotive ADAS to communications and high-performa...

5
256-bit vector word length, dual-core ARC VPX3 DSP IP with integrated hardware safety features for automotive
The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS applica...

6
3DES-ECB 1 Billion trace DPA resistant cryptographic accelerator core
Rambus Crypto Accelerator 3DES-ECB Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumpti...

7
512-bit dual-core vector DSP IP

The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS appl...

8
ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

9
ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

10
AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
Rambus Crypto Accelerator AES-AE-Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

11
AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the powe...

12
AES CCM/GCM Engine
The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O reg...

13
AES Engine
The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

14
AES GCM/XTS Engine
The EIP-38 - AES/GCM/XTS/LRW Engines are specifically suited for next generation processors deployed in networking and storage appliances that need to support combinations of AES (with its regular fee...

15
AES Key Wrap Engine
The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a r...

16
Arasan Chip Systems - SoC Design Services
Arasan Chip Systems is a leading provider of Total IP solutions for mobile storage and connectivity applications. Arasan’s high-quality, silicon-proven Total IP Solutions include Digital IP Cor...

17
ARC AS200 Audio Family - Efficient Single/Dual Core Audio Processors, Optimized Codecs

Synopsys offers an extensive portfolio of audio codecs that are available for use with the DesignWare® ARC® EMxD and the ARC HS4x families of processors. The ARC audio codecs facilitate a range of...

18
ARC EM22FS safety processor
The DesignWare® ARC® EM22FS Safety Processor simplifies development of safety-critical applications and accelerates ISO 26262 certification of automotive system-on-chips (SoCs).

19
ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications

DesignWare EV Embedded Vision Processors provide high-performance processing capabilities at a power and cost point low enough for embedded applications, while maintaining flexibility to support an...

20
ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications

DesignWare EV Embedded Vision Processors provide high-performance processing capabilities at a power and cost point low enough for embedded applications, while maintaining flexibility to support an...

21
ARC HS46FS, HS47DFS, and HS48FS Functional Safety Processors

The Synopsys ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety Processors simplify development of high-performance safety-critical applications and accelerate IS...

22
ARC HS47D with ASIL-B and ASIL-D support including dual-core lockstep for automotive functional safety applications
The DesignWare ARC HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors simplify development of high-performance safety-critical applications and accelerates ISO 262...

23
ARC HS48 quad-core processor with ASIL-B/ASIL-D support for functional safety applications
The DesignWare® ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors simplify development of highperformance safety-critical applications and accelerates ISO 26...

24
ARC Processors for Audio

The DSP-enhanced Synopsys ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA). The DSP-enhanced ARC processor famili...

25
ARC VPXxFS DSP Processor for Automotive

The ASIL B, C and D compliant Synopsys ARC® VPXxFS DSP IP is a family of VLIW/SIMD processors enabling automotive system-on-chip (SoC) designers to accelerate advanced driver assistance systems...

26
ARC4 Engine
The EIP-44 is the IP for accelerating the ARC4 stream cipher algorithm (used for legacy SSL & IPsec).

27
ARIA Engine
The EIP-11 ARIA algorithm, as specified in RFC 5794. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling and GHASH. Besides the...

28
Automotive ASIL B Compliant tRoot Hardware Secure Module IP
The ASIL B compliant DesignWare® tRoot™ Hardware Secure Module (HSM) for Automotive augments its comprehensive root of trust security solution with a suite of automotive documentation and hardware saf...

29
Automotive-grade controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

The complete silicon-proven DesignWare® IP solution, consisting of configurable digital controllers, PHYs, IP Prototyping Kits and verification IP, is designed to meet all required features of ...

30
Automotive-Grade DesignWare CSI-2 Device Controller IP
Integrating advanced peripherals such as multi-megapixel cameras and higher resolution screens into next generation devices brings new challenges to the industry in terms of power, time-to-market and ...

31
Automotive-Grade DesignWare MIPI CSI-2 Controller IP
The DesignWare® MIPI CSI-2 Host Controller IP is a fully verified and configurable controller IP that implements all protocol functions defined in the MIPI CSI-2 specification. The IP provides a high-...

32
Automotive-grade MIPI CSI-2 host/device controllers for high-speed serial interface between image processor and camera sensors

DesignWare® MIPI® IP solutions enable the interface between system-on-chips (SoCs), application processors, baseband processors and peripheral devices. Synopsys' broad portfolio of MIPI...

33
Basic AES Engine
The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

34
Camellia Engine
The Camellia Engine implements the Camellia crypto algorithm, as specified in Specification of Camellia and RFC3713.

35
CAN 2.0B Bus Controller IP Core
The Controller Area Network (CAN) controller IP that implements the CAN2.0A, CAN2.0B as well as newer high performance Non ISO CAN-FD protocols.

36
CAN FD Bus Controller
The Controller Area Network (CAN) controller IP that implements the CAN2.0A, CAN2.0B as well as newer high performance Non ISO CAN-FD protocols.

37
CAN FD Light Bus Controller
Arasan’s Controller Area Network – Flexible Data-Light (CAN-FD Light) Controller IP implements the CAN FD-Light (CIA 604-1) protocol. It can be integrated into devices that require CAN-FD-Light connec...

38
CAN-XL

Arasan's most advanced CAN-XL Controller Core performs serial communication as per CAN 2.0, CAN-FD & CAN-XL Specifications. It also supports original Bosch Protocol & ISO 11898 specifications f...

39
ChaCha20 Engine
The EIP-13 ChaCha engine implements the ChaCha20 algorithm, as specified by [ChaCha]. The accelerators include I/O registers and an encryption/decryption core. Designed for fast integration, low gate ...

40
Circuit Camouflage Technology
Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-cloning protection for integrated circuits that has both...

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