Rambus Crypto Accelerator 3DES-ECB Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumpti...

Rambus Crypto Accelerator AES-AE-Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the powe...

The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O reg...

The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

The EIP-38 - AES/GCM/XTS/LRW Engines are specifically suited for next generation processors deployed in networking and storage appliances that need to support combinations of AES (with its regular fee...

The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a r...

The EIP-44 is the IP for accelerating the ARC4 stream cipher algorithm (used for legacy SSL & IPsec).

The EIP-11 ARIA algorithm, as specified in RFC 5794. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling and GHASH. Besides the...

The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

The Camellia Engine implements the Camellia crypto algorithm, as specified in Specification of Camellia and RFC3713.

The EIP-13 ChaCha engine implements the ChaCha20 algorithm, as specified by [ChaCha]. The accelerators include I/O registers and an encryption/decryption core. Designed for fast integration, low gate ...

Inside Secure Circuit Camouflage Technology, also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-cloning protection for integrated circuits that has both Commercial and Government Applications.

Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-cloning protection for integrated circuits that has both...

Inside Secure s Code Protection technology provides powerful automated software protection tools applicable across Mobile, IoT, Desktop and Server platforms.

Multimedia consumers expect easy and convenient access to the latest movies and TV shows wherever they are. Inside Secure enables content and service providers to securely deliver premium content to virtually any connected device the way users want it, online or offline, for use cases like video-on-demand, live and catch-up TV.

Inside Secure Content Protection Server is a fifth generation, interoperable, server-side Digital Rights Management (DRM) solution. Designed for wireless and wireline operators and service providers, Content Protection Server implements and extends multiple DRM technologies such as Microsoft PlayReady and Google Widevine DRM while providing common integration interfaces.

Providing superior security and tamper resistance, while being highly-cost effective. Our cores complement existing security implementations, and are ideal for preventing counterfeiting in a broad number of applications.

Rambus Crypto Accelerator SHA-2-Compact Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power cons...

Rambus Crypto Accelerator SHA-2-Full Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consump...

The CryptoManager Root of Trust is a fully-programmable hardware security core that protects against a wide range of attacks with state-of-the-art anti-tamper and security techniques to offer vendors security by design.

CryptoManager Security Engine is an in-device root-of-trust offered as an embedded hardware core, or as a software agent that can be implemented as a protected element in a trusted OS or directly in the high-level device OS for the secure provisioning of keys and features throughout the device lifecycle. This provides flexible implementation options and allows the CryptoManager Infrastructure to securely communicate with the device to provision keys and manage feature configurations in the supply chain and downstream ecosystems.

From chip management to device personalization to downstream feature provisioning, the CryptoManager security platform creates a trusted path from the SoC manufacturing supply chain to downstream service providers with a complete silicon-to-cloud security solution.

The Rambus CryptoManager Trusted Services support a variety of root of trust configurations via a hardware core or secure software, providing a scalable and flexible security solution. Our solutions s...

Designed to cost-effectively secure the broadcast and streaming of digital content, our CryptoMedia Content Protection Core provides pay TV operators and over-the-top (OTT) media providers robust secu...

Designed to protect high-value content, including 4K UHD and High Dynamic Range (HDR) programming, CryptoMedia Security Platform is a comprehensive suite of components that enables consumers to securely and easily store, copy and share premium content across multiple devices.

As part of Rambus award-winning silicon Intellectual Property (IP) product portfolio, the EIP-16 DES/3DES Engines implement the DES and 3DES algorithm, as specified in Federal Information Processing ...

Rambus DPA & Fault Injection Resistant AES-AE Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. AES-AE 1 Billion...

Rambus DPA & Fault Injection Resistant AES-ECB Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. AES-ECB 1 billi...

Our Cryptography Research division discovered Simple Power Analysis (SPA) and Differential Power Analysis (DPA), and developed fundamental solutions and techniques for protecting devices against DPA and related side-channel attacks, along with supporting tools, programs, and services.

Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. 3DES-ECB 1 Billion trace DPA resistant cryptog...

The DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC. These superior performance cores are easy to integrate into SoCs and FPGAs, providing robust side-channel resistance across different security and performance levels.

Rambus DPA Resistant PKEv2, PKEv3, PKEv4 Cryptographic Accelerator Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA.

Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. ChaCha20 Small DPA resistant cryptographic acc...

Rambus DPA Resistant Cryptographic Accelerator Core RBG (NRBG+DRBG) prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FPGA. RBG DPA resist...

Addressing the growing demand for readily available solutions that implement Differential Power Analysis (DPA) countermeasures, we developed a family of cryptographic cores and software libraries that...

DPA Resistant Software Libraries are a portfolio of unique products that provide performance optimized, quantifiable side-channel resistant security for embedded software systems with seamless integration across a wide range of applications. Our software libraries come in two main varieties, platform neutral C-code which is designed to run on any platform and optimized code for ARM Cortex platforms, providing a wide range of device design options.

Designed for leading security chip vendors, product companies, testing labs, and government organizations, the DPA Workstation analysis platform is the world’s premier side-channel analysis plat...