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All Silicon IP All Verification IP


  • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.1
  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Supports synchronous transfer at high speed mode with a bit rate of 80-1500 Mb/s
  • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
  • Spaced one hot encoding for Low power [LP] data
  • Supports ultra low power mode, high speed mode and escape mode
  • Supports one clock lane and up to four data lanes
  • Data lanes support transfer of data in high speed mode
  • Clock lane supports unidirectional communication
  • Supports High speed mode in Forward communication
  • PHY can be configured as a master or slave
  • One byte buffer is housed inside the core for both data-out and data-in paths
  • Activates and disconnects high speed terminators for reception and transmission
  • Supports error detection mechanism for sequence errors and contentions
  • Supports contention detection and turn-arounds
  • Testability for Tx, Rx and PLL
  • Has clock divider unit to generate clock for parallel data reception and transmission from/to the PPI unit
  • On-chip clock generation configurable for either transmitter or a receiver
  • Process & Foundry
  • Available in various foundry processes
  • No external (off-chip) components required
  • Can be ported to other processes

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