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Prototypes for pre-silicon system validation and hardware/software integration are essential for today s IP and SoC design teams. But development schedules are short and the brief time from RTL drop to test chip availability means that prototyping engineers are under tremendous pressure to deliver an operational prototype as fast as possible. ProtoCompiler is designed to minimize the effort and time required to bring-up and then deploy a Synopsys HAPS Series system for IP validation and software development with automation features for design planning, logic synthesis, debug, and connectivity to other verification environments like Synopsys VCS and ZeBu. The prototyping software is tightly integrated with the HAPS Series to deliver system performance unmatched by traditional budget circuit boards and FPGA design tools.


  • ASIC-to-FPGA migration of gated clocks speeds prototype bring-up
  • ASIC IP pre-validated with HAPS Series eases migration
  • Maximizes system clock speed
  • Manage HAPS daughter boards, stacked systems, interconnect, and memories
  • Find a partition solution in minutes with multi-million ASIC gate designs
  • Quickly assemble prototype modules into larger subsystems
  • Debug logic regardless of where design modules are assigned
  • Quickly import verification views and apply root cause analysis
  • Improve signal visibility and review longer periods of system operation
  • Combine virtual and FPGA-based prototypes for earlier prototype availability
  • Connect to transaction-based verification environments like Synopsys VCS


ProtoCompiler features are designed to accelerate the time to an operational prototype. This focus on bring-up time and schedule improvement has improved processing time by up to 50 percent over competitive alternatives. ProtoCompiler s technology employs an efficient data model, compilers, and partitioning tools to improve productivity of engineers using the Synopsys HAPS Series of FPGA-based prototypes. The system allows short iteration loops at the key processing points in the design flow that have traditionally been time-consuming to complete. Compile and conversion of ASIC designs has been accelerated with fast compilers and clock-conversion specially designed for the HAPS Series. Generating a feasible design fit across multiple FPGAs has been fully automated with a quarter-billion ASIC gate partition engine that delivers results in minutes versus hours. Reuse is a best-practice not only for ASIC design but for prototypes as well. The modular nature of the HAPS hardware architecture coupled with the incremental and hierarchical project management features of ProtoCompiler speed bring-up time by avoiding lengthy re-compile and place-and-route cycles. Prototype projects developed HAPS-DX and HAPS series systems are directly compatible and allow the prototyping team to integrate individual ASIC block or IP prototype projects into larger subsystems for full SoC validation scenarios. FPGA SYNTHESIS FOR HAPS
  • HAPS Clock Optimization (HCO)
  • DesignWare Library compatible
  • Timing-driven synthesis
  • System hardware targeting
  • High capacity design partitioning
  • Hardware integration and reuse
  • Seamless multi-FPGA support
  • Synopsys Verdi/Siloti data exchange
  • High-capacity debug sample storage
  • AMBA transactors
  • SCE-MI transactors

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