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Overview

The Navigator Console is the command line interface software included with the Navigator EJTAG probes for debugging Imagination Technologies MIPS-based cores. Navigator Console software is based on the Tcl/Tk scripting language. It provides control over all CPU resources including reading and modifying all registers, reading/writing memory and caches, controlling the translation lookaside buffer (TLB), on-chip SRAM, and shadow registers. It provides complete run control of the CPU including go, halt, single step, and setting/clearing software and hardware breakpoints. The Navigator Console provides control over hardware trace setup and viewing the resulting trace buffer when implemented on the processor.

Features

  • Supporting microAptiv, interAptiv, proAptiv and Series5 cores
  • Supporting MIPS32 cores including: 4K, 4KE, 4Ks, M4K, M4Kc, M14K, M14Kc, M14KE, M14KEc, 24K, 24KE, 34K, 74K, 1004K, 1074K
  • Supporting MIPS64 cores including 5K and 20K
  • Configuring the probe and target
  • Starting, stopping, stepping, and resetting the CPU (run control)
  • Loading code into memory, including flash programming
  • Setting and managing hardware and software breakpoints
  • Setting and managing complex breakpoints including primed, qualified, and tuples when available in the core
  • Viewing processor and system information
  • Viewing and modifying registers
  • Accessing and modifying memory
  • Viewing and manipulating the caches
  • Viewing and manipulating the translation lookaside buffer (TLB)
  • Setting triggers for hardware breakpoint conditions
  • Setting and controlling PDtrace or iFlowtrace acquisition modes
  • Viewing resulting on-chip or off-chip trace results in a readable format
  • Saving the trace buffer and trace setup information to files and later viewing that trace from a stand-alone dequeuer program
  • Controlling, configuring, and sending data to the EJTAG tap register
  • Viewing and modifying all registers (gprs and cp0s), memory-mapped registers (cm, cpc, gic, fdc), and user-defined peripheral registers down to the bit field level with the RegEdit GUI.
  • Supports virtualization features available in certain cores to view current guestID, view/modify guest CP0 registers, access guest memory, and view or modify the root and guest TLB entries
  • Supports virtualization triggers and trace; qualify triggers on a guestID, qualify trace for a specific guest, trace transitions between guests and record the guestID

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