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All Silicon IP

Overview

GUC has been delivering SoC design services on 0.5um to 16nm technology. GUC chip implementation solution resolves the challenges of multi-hundred-million gates design, GHz operating frequency, noise coupling at deep submicron, IR drop, ESD, design for manufacturing (DFM), and time to market requirements.

In addition to hierarchical physical synthesis, clock tree synthesis, static timing analysis with on chip variation (OCV), formal verification, multiple power domain/on-off domain verification, cross-talk fixing and prevention, and LVS/DRC, GUC’s advanced design flow, equipped with quick prototyping, automatic power design solution (power plan with IR & routability aware, power switch stitching for rush current and ramp-up time budget, power density checker for dynamic IR prevention), iterations reduction timing driven solution (Sign off customization for different PVT, stage base OCV (SBOCV), data flow analyzer, clock adjust cell (CAC), Hold free cell), DFM advisor (Lithographic Process Check (LPC), Virtual Chemical Mechanical Polishing (vCMP) check and fixing), etc., has been proven in hundreds of customers’ first silicon successes at deep submicron technology. On the other hand, GUC also delivers comprehensive design-for-testability (DFT) services including scan insertion, boundary scan, memory BIST with smart BIST grouping, memory repair, memory ECC solution, scan re-ordering, low power test pattern generation and compression, fault simulation services.



Besides, GUC provides IP hardening, IP test circuit/test pattern integration, SoC integration service from spec to GDSII or RTL to GDSII. GUC has successfully integrated complicated SoC and produced them in volume for hundreds of customer projects throughout the years. .



All above solutions are integrated and embedded on robust workflow management (WFM) system to achieve uncompromising design quality and excellent efficiency. .

Tech Specs

Country Taiwan
Vendor Type Turnkey Solution Provider
Main Core Competency Logic and High level Design , Physical Design
Application Domain Wireless Communication , Wireline Communication
Experience Technology Lower than 22nm Yes

Features

  • RTL-to-GDSII, Netlist-to-GDSII, Spec-to-GDSII
  • JTAG, Scan, ATPG, Memory ECC, Memory BIST, Memory Repair
  • IP test circuit/test pattern integration
  • Design porting, FPGA to ASIC / Cross Processes
  • ARM Processors / MIPS /Tensilica CPU Configuration/Hardening
  • Digital IP hardening
  • Hard IP (GDSII) merge
  • Foundation cell power/timing characterization for custom PVT sign-off
  • Foundation cell customization for low power and performance

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