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The EFLX-100 is an embedded FPGA IP core, for implementing reconfigurable logic, containing 120 Look-Up-Tables (LUTs) in Reconfigurable Building Blocks (RBBs), patented interconnect network, multiple clocks & scan: reconfigurable in-field at any time. The EFLX-100 core is available in 5 different configurations and 2 nominal voltages: each optimized for different performance-to-power requirements for different target applications.

Tech Specs

Geometry nm40
Target Process NodeLP/ULP


Technology: TSMC 40nm ULP CMOS Metal Utilization: 5 metal layers Nominal Supply Voltage (V): 0.9V & 1.1V Junction Temperature (C): -40 to 125 Sleep Mode Leakage Power (uW) for EFLX-100 core with eHVT Bit Cell: 1.4/2.5 (at 85C, 0.9V/1.1V, TT) Single Stage Control Logic Max Frequency (MHz): 186 ? 455 depending on options (TT, 85C, 0.9 or 1.1V) Area (mm2): 0.12 Clock Inputs: 1 to 8 Data I/O: 152 inputs and 152 outputs Total LUT s Logic Core: 120 DSP Core: 88 DSP MACs Logic Core: 0 DSP Core: 2 EFLX Array Size: 1x1 to 5x5 Design-for-Test Support: Yes LUT Utilization: >90% AXI/JTAG soft IP: Yes if requested 40LP Compatibility: Yes

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