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Overview

The EFLX-2.5K Logic IP core is an embeddable FPGA IP core each containing 2,520 Look-Up- Tables (LUTs) in Reconfigurable Building Blocks (RBBs) and 20Kb RAM, patented interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time. It is SILICON PROVEN. The EFLX-2.5K DSP core replaces some RBBs with 40 DSP MACs (22x22 multiplier with 48 bit accumulator). It is compatible with the Logic core so it can be mixed with it in arrays. The cores can be used standalone or arrayed in square, rectangular or L shapes up to 7x7. Our patented area-efficient hierarchical interconnect network needs fewer metal layers than conventional FPGAs, enabling the integration of EFLX cores in high volume chips.

Block Diagram

Tech Specs

FoundryTSMC
Geometry nm28
Target Process NodeHPC/HPM/HPCP

Features

Technology: TSMC 28nm HPM/HPC CMOS Metal Utilization: 6 metal layers Nominal Supply Voltage (V): 0.9, 1.0 Junction Temperature (C): −40 to 125 Leakage Power (mW): 3 (at 25C, 0.9V, TT) Single stage control logic Max Frequency (MHz): 525 (at 125C, 0.81V, SS) Area (mm2): 1.20 Clock inputs: 1 to 8 Data I/O: 632 input & 632 output Look-up Tables (2 independent out per LUT) Logic/Mem Core: 2,520 DSP Core: 1,880 Distributed Memory (Kb) Logic/Mem Core: 20Kb DSP Core: 1Kb DSP MACs 0 40 Logic/Mem Core: 0 DSP Core: 40 Array: 1?1 to 7?7 Design-for-Test Support: Yes LUT Utilization: >90%

Deliverables

Front-end Design view (with NDA) Encrypted Verilog Model LIB Footprint LEF Detailed datasheet & DSP User?s Guide Silicon validation report EFLX Compiler evaluation version Back-end Design Views (with License) Verilog Model GDS-II CDL/Spice netlist Integration guidelines Integration assistance as needed EFLX Compiler bitstream generation version

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