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Menta® eFPGA Core® IP is based on a high-density embedded programmable logic architecture designed to be used in SoC or ASIC. Using an eFPGA Core provides design flexibility and reduces time-to-market by enabling lifetime re-programmability. The technology allows logic to be changed after manufacturing, reduces the number of chip re-designs and amortizes chip development costs over several design derivatives. This is the ideal solution for semiconductor companies wanting to add configurability to their end products. The eFPGA Core IP is silicon proven on several CMOS process (planar and FinFet).


Menta eFPGA IP is made of 3 blocks: Logic Block, Memory Blocks and Application Blocks. Logic Blocks: these contain the patented Menta LUT which have been designed to allow the best speed and resources usage trade-off. Customers can chose any number of logic blocks

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