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The Cadence® Tensilica® ConnX BBE32EP enhanced performance digital signal processor (DSP) core establishes a new standard in high-performance, low-power digital signal processors specifically designed for high-performance baseband processing. Optimized for complex number processing, the Tensilica ConnX BBE32EP core offers significant improvements in maximum frequency and algorithmic performance while reducing both silicon area and power consumption versus earlier generations of DSPs. The ConnX BBE32EP is the first DSP truly suitable for inclusion in both infrastructure and user equipment applications. Easily optimized through check box options, the Tensilica ConnX BE32EP along with the larger Cadence Tensilica ConnX BBE64EP provides unprecedented flexibility in implementing systems at power consumption levels that significantly reduce the need for hardware accelerators.


  • High performance, low power over a broad range of algorithms including support for LTE Advanced, LTE, HSPA+, and Wi-Fi including multiple-input and multiple-output (MIMO)
  • Fast baseband development through familiar C programming with general-purpose digital signal processing and 2G/3G/4G/Wi-Fi specific library support
  • Full support for hardware/software co-design
  • Easy integration into system SoC simulations with functional, cycle-accurate, and hardware pin-level models
  • Configurable instruction set with 12 predefined, pre-verified vector packages, from fast Fourier transforms (FFTs) to Advanced Precision arithmetic
  • Extensible instruction set support through the TIE language
  • Scalable with customized FIFO, port, and lookup interfaces


  • 32-way multiplier-accumulator (MAC), dual 16-way arithmetic logic unit (ALU) single instruction, multiple data (SIMD) engines
  • 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
  • 32-bit scalar ALU
  • Advanced Precision for matrix inversion and divide operations
  • Optimized instructions for:
    • Complex arithmetic
    • Polynomial evaluation
    • Matrix multiplication
    • Block floating point
    • Bit-oriented operations
    • Vector compression and expansion
    • Predicated vector instructions
  • Wide memory bandwidth
    • 256-bit load/store and 256-bit load units
  • 10-stage DSP pipeline
  • High-performance C/C++ compiler with automatic vectorization of scalar C and full support for vector data
  • TI intrinsic support; rich application libraries

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