www.design-reuse-embedded.com
Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Embedded Processing  > Memory
Download Datasheet        Request More Info
All Silicon IP

Overview

The MemMax Memory Scheduler is an intelligent DRAM access scheduler designed for use with an OCP compliant memory controller and Sonics family of on-chip communications solutions. Ideal for high-bandwidth applications, MemMax s sophisticated thread-based pipelining and advanced arbitration schemes reduces interconnect over-design and redundancy. By decoupling the functionality of the SoC from the DRAM, MemMax also encourages adoption of the DRAM technology that offers the best cost and performance value.

Features

  • Improved scheduler allows for frequency up to 500MHz (in TSMC 65nm GP libraries)
  • Support for XOR (needed by DDR3) and BLCK (2D) burst sequences
  • Pipelined threadbusy support eases timing closure process
  • Multi-threaded architecture enables easy scalability without redesign of memory subsystem
  • Performs dynamic priority management among threads to affect internal and up-stream interconnect arbitration
  • Implements bandwidth metering and rate allocation on each thread

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.