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The MemMax Memory Scheduler is an intelligent DRAM access scheduler designed for use with an OCP compliant memory controller and Sonics family of on-chip communications solutions. Ideal for high-bandwidth applications, MemMax s sophisticated thread-based pipelining and advanced arbitration schemes reduces interconnect over-design and redundancy. By decoupling the functionality of the SoC from the DRAM, MemMax also encourages adoption of the DRAM technology that offers the best cost and performance value.


  • Improved scheduler allows for frequency up to 500MHz (in TSMC 65nm GP libraries)
  • Support for XOR (needed by DDR3) and BLCK (2D) burst sequences
  • Pipelined threadbusy support eases timing closure process
  • Multi-threaded architecture enables easy scalability without redesign of memory subsystem
  • Performs dynamic priority management among threads to affect internal and up-stream interconnect arbitration
  • Implements bandwidth metering and rate allocation on each thread

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