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D15/D15F are the first dual-issue superscalar AndesCore™ processors. Both processors feature over 130 compiler friendly, general purpose DSP and SIMD instructions that enable easy DSP algorithm programming in C/C++. D15/D15F comes with a variety of configuration options, including MMU, cache and local memory. The 64-bit data buses for caches, local memory and the main bus provide the bandwidth needed for instruction fetch and data access. D15F includes a built-in IEEE-754 compliant floating point unit that enhances the floating point processing capability. D15/D15F is designed for diversified performance-driven applications on the embedded Linux, Real-Time OS or bare metal environment.
  • Dual-issue pipeline
  • > 130 DSP extension instructions
  • Caches for fast code and data accesses
  • Local Memories for deterministic code and data accesses
  • Built-in IEEE754-compliant FPU coprocessor (D15F)
  • Memory Management Unit (MMU) for Linux
  • 64-bit AXI4/AHB/AHBx2 bus interface
  • Benefits

    AndeStar™V3 Architecture
    • Better performance for modern compiler
    • Smaller code size
    • Trade-off between core size and performance requirements
    • Faster SW development and easier maintenance
    • Efficiency and protection with a dedicated kernel stack pointer
    • Better program code size and performance
    • More performance
    • Quick identification of interrupt sources and fast assignment of service routines
    • Full range address space
    • Easy to program and friendly to compiler

    CPU Core

    • Superior performance-per-MHz
    • Capable of processing two instructions in parallel to accelerate performance
    • Digital signal processing performance enhancement
    • Better performance for branches
    • Stack size determination and runtime overflow error detection
    • Simplification SoC design and debugging
    • Program code performance tuning
    • Basic read/write/execute memory protection with minimun cost
    • More performance
    • Lower power
    • Simplified SoC integration
    • Faster context switch for real-time applications
    • Better performance-efficiency
    • Peak power consumption reduction
    • Better power management efficiency
    • For floating point application

    Memory Subsystems

    • Higher performance for large program size
      • Accelerating accesses to slow memories
      • Flexible cache configurations
      • VIPT for low power on context switch
    • Higher efficiency for program execution
      • Flexible size selection to fit diversified needs
    • Code and data integrity protection
    • Efficient data transfer
    • User-selectable bus interface for optimal efficiency


  • Biometric devices
  • Wireless modem
  • Voice/speech recognition
  • Global Position System (GPS)
  • Unmanned Aerial Vehicle (UAV)
  • Sensor device/Sensor hub
  • Advanced motor control
  • Block Diagram


    AndeStar V3 Architecture
    • 21st-century RISC instruction set
    • 16/32-bit mixable opcode format
    • 32 general-purpose registers
    • All-C Embedded Programming
    • Shadow stack pointer
    • Radix-4 hardware divider
    • Aligned and unaligned load/store multiple word instructions and post-increment load/store memory accesses
    • 64-bit load/store unit
    • Direct support of up to 32 interrupts with programmable priority levels
    • 4G address space
    • Memory mapped IO

    CPU Core

    • 3.36 DMIPS/MHz
    • 5.41 CoreMark/MHz
    • 6-stage dual-issue pipeline
    • DSP extension instructions
      • > 130 instructions
      • Zero-overhead loop
      • Saturation and Rounding
      • Fractional Q31/Q15/ Q7 data types
      • Integer U32/U16/ U8 data types
      • 16-bit and 8-bit SIMD instructions
      • 64-bit signed/unsigned addition & subtraction
      • GCC intrinsic functions to use in C
    • GCC vector data type for SIMD instructions
    • Extensive branch predication (BTB and RAS)
    • Hardware stack protection
    • Processor state bus
    • Performance monitors
    • Memory Management Unit
      • 32/64/128-entry 4-way set-associative main TLB
      • Hardware page table walker
      • Support two groups of page size (4KB & 1MB, 8KB & 1MB)
    • Memory Protection Unit - 8 memory protection regions
    • Fast multipliers (1 cycle)
    • Extensive clock gating and logic gating

    Memory Subsystems

    • I & D Cache
      • Virtually Indexed and Physically Tagged (VIPT)
      • Size:4KB to 64KB, line size: 32B
      • Set associativity: 2-way (I-Cache), 4-way (D-Cache)
    • Optional External Instruction and Data Local Memory
      • Size: 1KB to 16MB
      • 64-bit ILM: program code, data and IO
      • Dual 32-bit DLM: program data
    • ECC or Parity for soft-error protection (Parity protection is valid for D-Cache and DLM only)
    • Optional 1D/2D DMA with 64-bit transfer
    • BIU supports 64-bit AXI4/AHB/AHB2

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