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Overview

Briliante is Brite s Mx-based SoC solution for customers fast integration and reliable design. Based on customers target specification, Brite can complete the RTL design for synthesis, including automatically generated test cases for verification, within 1~3 days depending on the architectural complexity. Besides, this solution eliminates the risk from manual connection and programming through simple and parameterized configuration mechanism. Briliante can integrate Arm Cortex-M0, Cortex-M3 or Cortex-M4 processors with various digital peripherals through ARM AMBA AHB and APB standard bus interfaces. The multilayer AHB bus matrix is chosen for high efficiency and high throughput scenarios. The number of each peripheral can be configured to achieve desired features, which includes embedded flash interface, SRAM, I2C, UART, SPI, Timer, WDT, PWM, CAP, GPIO, etc. In order to provide complete solution, Brite also customizes analog IP (ADC, POR, LDO, ROSC, etc) in SMIC s processes based on the requirement of the whole chip. Briliante modular approach enables rapid silicon realization. Development time is correspondingly reduced by as much as 75% compared to the development from the scratch. The Briliante architecture and methodology is tested and silicon verified. The turnkey solution includes a comprehensive set of software libraries, protocol stacks, and development tools.

Applications

  • Controllers for home appliances, industrial control, touch screen, meters, etc.
  • General purpose controllers embedded in SoC

Features

  • M0 SoC test chip and verification systems are available
  • Multiple cores can be adopted including Cortex-M0+, Cortex-M0, Cortex-M3, Cortex-M4
  • Multiplayer AHB bus-matrix is adopted
  • Arbitrary number of general APB peripherals including UART, I2C,SPI,PWM etc..
  • Flexible IO MUX scheme
  • Embedded flash controller + programmer prototypes
  • Standard development environment (Keil MDK, ARM RVDS,DS5)
  • Application IP can be easily integrated such as USB,CAN, Ethernet MAC..
  • Evaluation system including FPGA boards and test chip boards
  • Mature Analog IP portfolio (SAR ADC,POR,LDO,OSC)
  • Test cases and verification environment automatically generating
  • Low power consumption in deep power down mode
  • Peripheral sleep and CPU sleep modes implemented with optional wake-up circuits

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