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IDesignSpec™ is an award winning product that helps IP/SoC design architects & engineers to create simple yet powerful specification in MS Word, Excel, Libre Office or plain text. The specification is content aware and any conflict in address is checked and highlighted in the specification itself. Any change done in the specification automatically gets translated into code.

IDesignSpec (IDS) captures simple as well as special registers, signals, interrupts, sequences, and generates synthesizable RTL code and interfaces for ARM AMBA® buses like AXI, AHB, APB, AHB3Lite. IDS provides the C/C++ header files and firmware files and enable SW team to develop device driver at an early stage of the design cycle.

View IDesignSpec UVM Register Generator, IP-XACT Reader/Writer Solution Reference


The AMBA AXI4FULL is suitable for high-bandwidth and low-latency designs. It provides high-frequency operation, without using complex bridges.


  1. Configurable bus width up to 1024 bits
  2. Write/Read transactions with multiple latency in slave
  3. Support simultaneous write and read
  4. Support Bursting (incrementing and wrapping)
  5. Out-of-order transactions not supported

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