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AndesCore™ N25 is a 32-bit CPU IP core based on AndeStar™ V5m Instruction Set Architecture, which support RISC-V RV32IMAC extensions from the latest developments in computer architecture and boosted by Andes Technology s own performance enhancement instructions. Designed with a fast and efficient 5-stage pipeline, N25 reserved one full cycle time for embedded SRAM such as Caches and Local Memories to match with the CPU core which operates fast as over 1 GHz with 28nm process technology. Performance options includes such as high speed or small gate count multiplier, and choice of Dynamic Branch Prediction with Branch Target Buffer, Branch History Table and Return Address Stack. Design features includes AXI or AHB bus master port with clock frequency flexibly configurable as fraction of CPU clock, AHB slave port for direct bus master accesses to Local Memories, Vectored interrupt dispatch for the integrated Platform-Level Interrupt Controller (PLIC), and Exception Redirection that automatically triggers debugging events.
  • AndeStar V5m 32-bit Instruction Set Architecture
  • RISC-V compliant plus Andes performance enhancement extensions
  • Branch Prediction with large history buffers to accelerate complex programs
  • Individually configurable Caches and Local Memories for Instruction and Data
  • Native support of AXI/AHB bus master and AHB bus slave ports
  • Fast and compact design to reach over 1 GHz at 28nm
  • Product packages of N25 with CPU Subsystem, and N25 with AHB Platform
  • Benefits

    AndeStar V5m Architecture
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
  • Instructions to enhance performance and code size
  • Andes exclusive performance and functionality enhancements
  • For compact code density
  • For better code size and performance
  • Embedded systems with privilege protections

    CPU Core

  • 2.86 DMIPS/MHz 3.45 CoreMark/MHz
  • 5-stage pipeline, with a full-cycle reserved for critical SRAM accesses
  • Extensive Branch Predication features
    • Branch Target Buffer (BTB): 32, 64, 128 or 256-entry
    • Branch History Table (BHT): 256-entry, with 8-bit branch history
    • Return Address Stack (RAS): 4-entry
  • StackSafe hardware stack protection
  • Multiplier options
    • Fast multipliers: pipelined, 2-cycle
    • Small multiplier: producing 1, 2, 4, or 8 bits per cycle

      Memory Subsystems

    • I & D Cache
      • Size: 8KB to 64KB
      • Set associativity: Direct-mapped, 2-way or 4-way
    • ILM & DLM
      • Size: 4KB to 16M
      • Bus masters accesses by AHB slave port
  • Applications

  • Networking and Communications
  • Unmanned Aerial Vehicle
  • Virtual and Augmented Reality
  • Video and Image Processing
  • Storage and Media Streaming
  • Block Diagram


    AndeStar V5m Architecture
  • RISC-V RV32IMAC Instructions
  • Andes Extended Instructions
  • 16/32-bit mixable instruction format
  • 32 general-purpose registers
  • Machine (M) and User (U) Privilege levels

    CPU Core

  • 2.86 DMIPS/MHz 3.46 CoreMark/MHz
  • 5-stage pipeline, with a full-cycle reserved for critical SRAM accesses
  • Extensive branch predication features
  • StackSafe hardware stack protection

    Memory Subsystems

  • I-Cache & D-Cache
    • Size: 8KB to 64KB
      Set associativity: Direct-mapped, 2-way or 4-way
  • ILM & DLM
  • Soft-error protection: ECC or parity for I-Cache and D-Cache, ILM and DLM with SRAM interface
  • Bus master port: AXI with 64-bit data or AHB with 64 or 32-bit data
  • Bus save port: AHB with 64 or 32-bit data, for ILM/DLM accesses
  • Core/bus clock ratio of N:1

    Platform-Level Interrupt Controller (PLIC)

  • Implements RISC-V PLIC specification
      Up to 1023 PLIC interrupt sources
      Up to 255 PLIC interrupt priority levels
      Up to 16 PLIC interrupt targets
  • Enhanced interrupt features
  • Debug Support

  • Implements RISC-V debug specifications
  • 5-wire JTAG Debug Port
  • Embedded Debug Module with up to 8 triggers
  • Exception redirection support
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