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Overview

Hantro G1 multi-format hardware decoder brings an unprecedented level of format and resolution support to enable all kinds of video applications. It is also the first hardware decoder in the market to support full WebM (VP8) decoding, significantly extending the video playback time of Internet-connected and HTML5-enabled battery operated devices. Intended for chips powering multimedia devices (mobile phones, portable media players, tablets/netbooks, DVD/Blu-ray players, STB, car infotainment, etc.), Hantro G1 is built on silicon-proven designs deployed in hundreds of millions of chips worldwide and thus, provides semiconductor manufacturers with a minimal risk solution for integrating high performance video capability into their chips. Hantro G1 decoder design is exceptionally fast, requiring around 100MHz clock frequency to decode 1080p video at 30 fps, and can achieve 60fps decode for 1080p video in real life conditions. The core supports unlimited multi-format, multi-channel decoding, enabling simultaneous playback of up to ten SD streams. It uses unique pre-fetching and buffering mechanisms to enable smooth operation with low-end SDRAMs, realizing significant savings in power and overall chip design and manufacturing costs. Hantro G1 is market s lowest power video decoding solution consuming less than 30 mW for full HD video decoding, and just around 5 mW for SD video decoding.

Benefits

  • H.264 Baseline, Main and High Profiles, levels 1 - 4.1
  • MVC Stereo High Profile
  • VP8 for WebM and WebP support
  • MPEG-4 Simple and Advanced Simple Profiles, levels 0 - 5*
  • Sorenson Spark and H.263 Profile 0, levels 10 - 70
  • WMV9 / VC-1 Simple, Main and Advanced Profile, levels 0 - 3
  • MPEG-1&2 Main Profile, levels low, med and high
  • RealVideo 8/9/10
  • DivX 3/4/5/6 support Home Theatre Profile Qualification
  • VP6, VP7
  • AVS Jizhun Profile
  • JPEG and MJEPG support

Tech Specs

Market SegmentVideo

Features

  • All algorithms in HW minimal CPU load
  • Minimal power consumption functional level clock gating and synthesis time clock gating (>90% of registers under gating)
  • Integrated image/post-processing block
  • Extensive resolution, format and feature configurations
  • HW sharing for multi-instance support
  • Three buffering options for minimizing memory bandwidth
  • High latency and non-sequential access delay resilience
  • Feature fusing for manufacturing different chip variations

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