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Overview

The Arm® Cortex® processor is the smallest, lowest power Arm multicore processor capable of delivering the internet to the widest possible range of devices: from ultra low cost handsets, feature phones and smart mobile devices, to pervasive embedded, consumer and industrial devices. Both the extremely area and power efficient Cortex-A5 uniprocessor and the scalable Cortex-A5 MPCore multicore processors are supported by a rich set of features and Arm v7 architectural functionality to deliver a high-performance and low-power solution across both application specific and general purpose designs. The Cortex-A5 processor includes TrustZone® security technology along with a NEON® multimedia processing engine first introduced with the Cortex-A8, processor. NEON technology is a 128-bit SIMD (Single Instruction, Multiple Data) architecture extension for the Cortex-A series processors, providing flexible and compelling acceleration for intensive multimedia applications. Cortex-A processors are used in applications that have high-compute requirements, run rich operating systems and deliver interactive media and graphics experience from the latest technological mobile internet must-have devices such as SmartPhones, handsets, tablets and ultra-portable netbooks or SmartBooks, to automotive infotainment systems and next generation digital TV systems.

Features

Single issue microprocessor core (limited dual issue of branches):
  • 8-stage main integer pipeline
  • Optional NEON and Floating Point Units
Optimized for industry leading power efficiency and area Arm v7 architecture compliant including:
  • Thumb(R)-2 technology for greater performance, energy efficiency, and code density
  • NEON signal processing extensions to accelerate media codecs such as H.264 and MP3
  • Jazelle DBX and Jazelle RCT Java-acceleration technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC), and reduce memory footprint by up to three times
  • TrustZone technology for secure transactions and Digital Rights Management (DRM)
Optimized Level 1 Caches
  • Performance and power optimized 40LP RAMs available from Arm
  • Configurable from 4K to 64K
Dynamic Branch Prediction
  • Enabled by branch target and global history buffers
  • Achieves 95% accuracy across industry benchmarks
  • Limited dual issue of direct branches provides uplift in performance
Memory System
  • Single-cycle load-use penalty for access to the L1 cache
  • Optimized AMBA AXI memory system provides up to 3x the memory bandwidth off Arm1176JZ-S
  • Support for multiple outstanding transactions to the external memory to fully utilize the CPU
Maturity: Shipping is many finished parts Target Process Node: any

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