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All Silicon IP

Overview

The Arm® Cortex®-R real-time processors offer high-performance computing solutions for embedded systems where reliability, high availability, fault tolerance, maintainability and real-time responses are required. The Cortex-R series processors provide fast time-to-market through proven technology shipped in hundreds of millions of products and leverages the vast Arm Ecosystem and global, local language, 24/7 support services to ensure rapid and low risk development. There are many applications requiring the key Cortex-R series attributes of:
  • High performance: Fast processing combined with a high clock frequency
  • Real-time: Processing meets hard real-time constraints on all occasions
  • Safe: Dependable, reliable systems with high error resistance
  • Cost effective: Features for optimal for performance, power and area
The Cortex-R4 processor, is designed for implementation on advanced silicon processes with an emphasis on improved energy efficiency, real-time responsiveness, advanced features and ease of system design. The processor provides a highly flexible and efficient two-cycle local memory interface, enabling SoC designers to minimize system cost and energy consumption.

Features

Fast - high performance
  • Power-efficient, 8-stage dual issue pipeline with instruction pre-fetch and branch prediction
  • Arm v7R architecture - Thumb-2 / Arm instructions
  • Hardware divide, SIMD, DSP, SP/DP FPU options
  • Harvard I + D caches, 64-bit AMBA AXI-3
Deterministic - fast interrupt response
  • Vectored Interrupt Controller port
  • Low Latency Interrupt Mode (LLIM) to accelerate interrupt entry whenever possible without waiting for the current instruction or memory access to complete
  • Tightly-Coupled Memory system which provides a second level-1 memory besides the cache for storing critical code and data such as interrupt service routines which can then be immediately executed without waiting for cache evictions and fetches from main memory
Reliable - error handling built into core
  • Memory Protection Unit
  • ECC and Parity protection on L1 memories
  • Dual core lock-step configuration
  • Cost-effective and low cost of ownership
  • Synthesis configurable for optimum PPA
  • CoreSight debug and trace
Maturity : Shipping in many parts Target Process Node : any

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