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ChipArchitect for SoC and ASIC is a web browser-based tool for creating a design architecture, estimating it, and selecting a mapping to any one of 15 supported nodes in a wirebond or flip-chip packaged device. ChipArchitect for SoC contains advanced estimation and layout-creating floorplan detail good enough for your backend. Additionally, our SoC Economics handle package selection and pricing for your NRE and device costs. Featuring wafer cost & yield modeling fed from floorplanning, ChipArchitect for SoC helps visualize the breakdown of die, package, assembly, and test costs.


  • Cut-and-paste addition of blocks to create complex architectures
  • Built-in catalog of over 1M SemantIC I/O channels and IP
  • External IP catalog of over 14,000 parts from 400+ vendors
  • Ability to read in internal IP models and RTL estimates
  • Process-specific models of I/O, Standard Cells, Memory, and more
  • Process-specific models of SERDES, PHY, PLL, ADC, DAC, and more
  • Nodes from 14nm to 0.35?m with process, FinFET, library variants
  • Built-in die estimation, auto floorplan, block diagram generation
  • Complete built-in Package, Wafer, Mask, Yield loss, and cost database
  • Mask, proto lots, probe cards, and test data for complete NRE costing
  • Package costs, thermal calculation, yield, bonding or flip-chip

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