ChipArchitect for SoC and ASIC is a web browser-based tool for creating a design architecture, estimating it, and selecting a mapping to any one of 15 supported nodes in a wirebond or flip-chip packaged device.

ChipArchitect for SoC contains advanced estimation and layout-creating floorplan detail good enough for your backend. Additionally, our SoC Economics handle package selection and pricing for your NRE and device costs. Featuring wafer cost & yield modeling fed from floorplanning, ChipArchitect for SoC helps visualize the breakdown of die, package, assembly, and test costs.