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With the increased use of smaller geometry semiconductor processes and FinFET transistors, the on-chip interconnect has become a prime source of timing closure issues. These issues are usually found late in the design process which causes schedule slips and delayed time-to-market. Design teams currently deal with these issues by manually inserting pipeline stages in the chip netlist through an engineering change order (ECO) process.

PIANO 2.0 solves back-end timing problems with technology that works earlier in the SoC design flow, thereby reducing schedule risk. Its new technology introduces the concept of physical interconnect distance to customers using Arteris FlexNoC and Ncore interconnect products. First, PIANO calculates the length of individual interconnect links and traces, and then uses information about the semiconductor technology process and performance targets to automatically add interconnect pipelines to close timing. Then PIANO helps validate this timing closure scheme with the physical synthesis capabilities of the Synopsys or Cadence tool chains.


  • Slashes the time needed to close timing compared to manual pipeline insertion methodologies, which reduces overall schedule risk. With a well-defined methodology, interconnect timing can be closed in as little as 24 hours.
  • Shrinks interconnect area by 10-15% compared to manual pipeline insertion methodologies, which over-provision pipeline stages
  • Decreases interconnect power consumption due to less pipeline logic and use of fewer low voltage threshold (LVT) cells
  • Provides seeding of pipeline stage locations which allows place and route tools a better starting point, eliminating costly place and route cycles


  • Automated interconnect timing closure for both cache coherent and non-coherent interconnect subsystems
  • Generation of a meta-floorplan from an IP list to provide timing closure guidance during the SoC architectural development phase
  • Input and output of production floorplans in LEF/DEF and TCL formats
  • Automatic pipeline insertion with advanced features:
    • Edit timing closure parameters to optimize individual timing paths
    • Automatically account for crossing between multiple frequency and voltage domains
    • Automatically generate timing closure analysis reports
  • Integrated with Synopsys' Design Compiler Graphical and IC Compiler II and Cadence's Genus and Innovus physical synthesis tool chains.

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