You are here : design-reuse-embedded.com  > Wireline Communication  > Interconnect
Download Datasheet        Request More Info
All Silicon IP


Tamba Networks offers a highly configurable Interlaken ILA and ILK core. The core is compliant with the Interlaken and Interlaken look-aside specifications, and targets FPGA and ASIC operation. The System BusWidth, Core BusWidth, and Lane Count are configurable. The System BusWidth is configurable from 1 Word to 16 Words, the Core BusWidth is configurable from 1 Word to 8 Words, and the LaneCount is configurable from 1 Lane to 32 Lanes. Note, 1 Word is 8 bytes.

The core runs cycle accurate, and is designed to run for example at 390 MHz in Altera SV-3. Every word delivers 25G of bandwidth, e.g. a solution with a 1 Word core can service 4x6.25G. Note, the Core bandwidth has to be equal to or greater than the SerDes bandwidth.


Lowest latency

We do not believe there is a lower latency solution in the market, and many customers are asking for it today.

Here are some examples.

  • 12x10G core latency (no serdes) 50nS in FPGA
  • 12x10G core latency (no serdes) 13nS in 28nM ASIC

Lowest gate count

Saving gates is always a benefit, and we are typically 3-4x smaller in gate count than most implementations. This can make a huge impact on ASIC die area or FPGA cost.

Huge timing margin

Often our cores will run in the slowest speed grade saving money, and compile with push button ease in minutes, significantly reducing development time by reducing time between iterations.

Fully Parameterized Solution

  • Configurable System Bus Width
  • Configurable Core Bus Width
  • Configurable Lane Count

Block Diagram


  • Complete MAC layer and PCS layer implementation compliant with Interlaken Protocol Specification v1.2 & Interlaken LookAside Protocol Specification v1.1
  • Compile Time Parameters;
    • Lane Count, 1-32 Lanes
    • Lane Rate, <6.25G or <25G
    • System BusWidth, 1-16 Words
    • Core BusWidth, 1-8 Words
    • Channel Count, 2-64K
    • Flow Control Count, 1-256
  • Runtime Configuration
    • Mode, packet mode or segment mode
    • BurstShort, Core BusWidth minus 1 to 128 Words
    • BurstMax, 8 words to 128 words
    • Enhanced Scheduling
    • Meta-frame Size
  • Supports up to 600G, e.g. 24x25G
  • In-band Flow Control & Out of band Flow Control
  • Status Messaging ??S layer Scrambling
  • MAC layer and PCS layer CRC generation and checking
  • 64/67 PCS encoding/decoding w/ DC balance
  • ILA Overhead insertion and extraction
  • Transmit clock and data rate decoupling with programmable asynchronous FIFO
  • Receive clock and data rate decoupling with asynchronous FIFO
  • Unidirectional or bidirectional operation
  • Lane Protection

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.