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All Silicon IP

Overview

For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL and IEC 61508 SIL levels. Data traffic must now be protected throughout the chip floorplan.

The Arteris FlexNoC Resilience Package provides hardware-based data protection for increased SoC reliability and functional safety.

In addition to providing functional-safety compliant IP, Arteris is working closely with YOGITECH S.p.A. to create a set of deliverables which can be used as a starting point in the preparation of ISO 26262 work products.

Implementing functional safety and data protection features in hardware is easier and less risky than software-only implementations.

Block Diagram

Features

  • ARM Cortex-R5 and Cortex-R7 processor port checking
  • Hardware duplication and redundancy
  • Custom ECC and parity generation and checking
  • Packet validity checking
  • Transaction timeout
  • Control register parity checking
  • Fault control and reporting

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