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For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL and IEC 61508 SIL levels. Data traffic must now be protected throughout the chip floorplan.

The Arteris FlexNoC Resilience Package provides hardware-based data protection for increased SoC reliability and functional safety.

In addition to providing functional-safety compliant IP, Arteris is working closely with YOGITECH S.p.A. to create a set of deliverables which can be used as a starting point in the preparation of ISO 26262 work products.

Implementing functional safety and data protection features in hardware is easier and less risky than software-only implementations.


Hardware IP functional safety is better than software because:
  1. Reduced Complexity – Software takes much more effort to develop and maintain than certifiable hardware IP;
  2. Improved Quality – Hardware IP is pre-tested and can be pre-certified while future software quality presents risk;
  3. Enhanced Control – Semi vendors set a baseline of safety features that must be implemented which is less risky than low grade software developed without knowledge, input or feedback.

Block Diagram


  • Data protection through error-correcting code (ECC) and parity checking
  • Out-of-the-box support for ARM Cortex-R5 and Cortex–R7 Processor Port Checking
  • Unit protection by duplication and redundancy
    • Similar to dual-core lockstep (DCLS) and often required for ASIL C or D systems as specified in the automotive ISO 26262 standard
  • Duplicate unit checkers and fault safety controller
  • Built in Self-Test (BIST) for resilience functions
  • Data protection by monitoring
  • Data packet integrity checkers
  • Easy partitioning of any SoC into safe and non-safe domains.

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