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Overview

Cadence provides a wide range of DSPs (digital signal processors) for Wireless Communication, Radar, SmartGrid applications as well as any application requiring digital signal or complex digital signal processing. Cadence Tensilica ConnX DSPs for Communication offer significant improvements in maximum frequency and algorithmic performance while reducing both silicon area and power consumption versus earlier generations of DSPs. The instruction set has been optimized for performance of DSP kernel operations such as FFT and FIR as well as matrix multiplies. Acceleration has been added for a wide range of critical wireless functions to deliver very high performance in those applications. A rich set of optional features and customization options enables designers to closely match the core with their specific application and project requirements. All our DSP solutions are supported with DSP libraries, offering optimized implementations of a wide variety of DSP functions.

Benefits

ConnX BBE16EP, BBE32EP and BBE64EP DSPs for scalable baseband processing The latest additions to the product line, the Cadence Tensilica ConnX BBE16EP, BBE32EP and BBE64EP enhanced performance DSPs for baseband applications are optimized for complex number processing. The 16-MAC BBE16EP, 32-MAC BBE32EP and the 64-MAC BBE64EP offer significant improvements in maximum frequency and algorithmic performance while reducing both silicon area and power consumption versus earlier generations of DSPs. They provide unprecedented flexibility in implementing systems at power consumption levels that significantly reduce the need for hardware accelerators. With identical architectures, N-way programming model compatibility, the BBExxEP family of DSPs provide you with significant design flexibility and an easy upgrade path when needed. The ConnX BBE EP DSPs are suitable for both infrastructure and user equipment applications. The ConnX BBE64EP is suited for multiple RF stream processing applications such as LTE-Advanced, 5G and other high-throughput MIMO systems such as 802.11ac. All of them can be easily optimized through check-box options. Legacy ConnX Communications DSPs
  • ConnX D2 – A flexible dual-MAC DSP, programmable in C
    The Cadence Tensilica ConnX D2 DSP provides approximately 20% higher performance than similar dual-MAC architectures. You benefit from the flexibility of C programming with assembly-level performance. It is an ideal solution for wireless communications, disk drives (including SSD), home entertainment devices, and computer peripherals – anything that requires a highly efficient 16-bit fixed-point DSP.
  • ConnX BBE16 – A full-featured high-performance 16-MAC DSP, programmable in C
    The ConnX BBE16 Baseband Engine combines an 8-way SIMD, 3-issue VLIW processing pipeline with a rich and extensible set of interfaces. This high-performance Cadence Tensilica DSP is built around a core vector pipeline made of 16 18bx18b MACs. These multipliers and associated adder and multiplexer trees enable operations such as FFT butterflies, parallel complex multiple operations, and signal filter structures. The results of these operations can be full precision or truncated/rounded/saturated and shifted to meet the needs of different algorithms and implementations.

Block Diagram

Features

Instruction set features
  • 16-way (BBE16EP), 32-way (BBE32EP) or 64-way (BBE64EP) multiplier-accumulator (MAC), dual 8/16/32-way arithmetic logic unit (ALU) single instruction, multiple data (SIMD) engines
  • 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
  • 32-bit scalar ALU
  • Advanced precision for matrix inversion and divide operations
  • Optimized instructions for complex arithmetic, polynomial evaluation, matrix multiplication, block floating point, bit-oriented operations, and vector compression and expansion
  • Predicated vector instructions
  • Wide memory bandwidth - 128/256/512-bit load/store and 128/256/512-bit load units
  • 10-stage DSP pipeline
  • High-performance C/C++ compiler with automatic vectorization of scalar C and full support for vector data
  • TI intrinsic support, rich application libraries
Configurable, extensible, scalable The ConnX BBE EP DSPs provide 13 pre-built vector options, which are included/excluded as checkboxes when defining a DSP from within the tools. These checkboxes result in seamless integration of a feature into the hardware, the compiler, the modeling tools, and the verification scripts. Using these capabilities, you can build a custom DSP without the large development schedule impact that a change in hardware design would normally involve. Integrating an optimized FFT solution is as simple as checking a box when configuring a ConnX processor. All of the verification and tool support is provided automatically as part of the tool chain. The ConnX BBE EP DSPs can be extended to support custom ports (general-purpose wire interfaces) and queues (FIFOs) for efficient connection to offload accelerators. These custom interfaces can be defined to match the interfaces of existing third-party IP. Buffered communication between two ConnX DSPs or between a ConnX DSP and an offload accelerator can be automatically implemented using Queue interfaces and are fully supported in programming and modeling tools. These interfaces are dedicated to the offload accelerator and offer single-cycle access. Thus, ConnX BBE EP DSPs can access hardware offload accelerators in a single-cycle deterministic operation, greatly reducing power consumption and without impacting the shared system bus. Application space-LTE, WCDMA/HSPA+, Wi-Fi, and Beyond ConnX BBE16EP, BBE32EP and BBE64EP DSP baseband engines are high-performance DSPs designed for next-generation communication systems such as LTE Advanced, 802.11ac, and DVB. Advanced precision options are specifically designed to meet the precision and performance requirements associated with advanced MIMO systems. In addition to vector-based filtering, FFT, and matrix capabilities, a fully-featured instruction set includes a full range of bit-oriented operations used in 3G systems such as UMTS, cdma2000, and 1xEV-DO. In this way, ConnX BBE EP DSPs excel at multi-standard physical layer processing, providing opportunities for hardware savings and a broader scope of applications than a dedicated fixed-hardware solution can provide. As physical layer (PHY) system developers move to advanced standards such as LTE-Advanced, they face the need for dramatic increases in performance from their processing platforms. ConnX DSPs meet this challenge with highly parallel vector engines. When processing needs scale beyond that of a single DSP, the ConnX BBE EP family provides smooth support for multi-core solutions. Multi-core solutions may involve other DSPs from the ConnX BBE family or extend into other Tensilica DSP processors. System designers also face considerable uncertainty as to the algorithmic implementation that will deliver the best performance. In fact, as systems become more diverse with wide-scale deployment of heterogeneous networks, a solution that works best for a microcell operating on a bullet train in Japan may be very different from one that will work best for a similar microcell operating in a subterranean pedestrian mall in Montreal. With a fully programmable software-based solution using the ConnX BBE64EP core, you could implement both solutions on a single platform, permitting it to evolve without going back for a re-spin of silicon for new functionality or bug fixes. The configurability and extensibility of ConnX DSPs also allows you to optimize the hardware for specific algorithms without the typical development delays associated with an ASIC design. Supported by a complete set of hardware and software tools Our complete set of tools includes a comprehensive instruction set simulator (ISS), which allows developers to quickly simulate and evaluate performance. The fast, functional TurboSimTM simulator option achieves speeds that are 40 to 80 times faster than the ISS for efficient software development and functional verification. System C and C-based system modeling can aid in full-chip simulations. The tool set includes a high-performance C/C++ compiler with automatic vectorization to support the VLIW pipeline. This comprehensive tool set also includes the linker, assembler, debugger, profiler, and graphic visualization tools. All major EDA flows are supported.

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