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TC1750 is a high throughput turbo/convolutional code encoder covering LTE, HSPA+, WiMAX 16e/m. It performs either convolutional turbo code (CTC) encoding or convolutional code (CC) encoding and rate matching for these three PHY layer specifications. The rate matching is flexible and can easily be used to execute HARQ mechanism.

Thanks to its high throughput architeture TC1750 is able to reach multi-Gbits/s throughput ranges with a single core instance:

  • up to 4 Gbits/s payload rate in LTE mode (with 500 MHz clock)
  • up to 1 Gbits/s payload rate in HSPA mode (with 500 MHz clock)
  • TC1750 can be used for both uplink and downlink. It can be implemented in Base Stations (from femtocells to large stations) or in the terminal SoC. ASIC and FPGA versions are available.

Block Diagram


  • Block-by-block change of physical layer mode (LTE/HSPA+/WiMAX), block length, rate matching parameters
  • Latency reduction by bank swapping
  • No external memory required
  • High throughput architecture
  • Silicon proven
  • ASIC Core: Verilog or VHDL RTL source code
  • FPGA Core available on all popular Altera, Lattice and Xilinx devices

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