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All Silicon IP

Overview

TC1770 is a IoT-optimized turbo decoder Core compliant with LTE Cat-0 / Cat-M (release 12 and release 13). This Core incorporates LTE rate matching and an efficient HARQ combining algorithm thats makes it ideal for operation in the range of low SNR. Its small footprint and low power consumption enable to build a very competitive solution compared to a software-only based solution. Three throughput profiles are available leading to throughputs in the range of 1 to 10 Mbits/s (depending on target process and clock frequency). Based on our silicon proven TC1700 Core engine, TC1770 is optimized for ASIC but can also be used on FPGA devices.

Block Diagram

Features

  • Maximal payload block size selectable at synthesis
  • Throughput range 1 - 10 Mbits/s
  • Efficient early stopping for reduced power consumption
  • Compacting of HARQ-combined streams - saves external HARQ buffer memory
  • Channel BER estimator
  • Flexible quantization level selectable at synthesis
  • Block-by-block change of configuration (block size, number of iterations, ...)
  • Clock gating scheme for low power consumption
  • AXI stream interface

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