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Overview

The fourth generation of the widely licensed CEVA-XC architecture, the CEVA-XC4500 is specifically optimized for next generation wireless infrastructure applications. The CEVA-XC4500 delivers highly powerful fixed point and floating point vector capabilities supplying the performance and flexibility demanded by next generation wireless infrastructure applications.

Benefits

- Optimized to address the processing requirements for a wide range of next generation wireless infrastructure applications - Enables modem design with minimum hardware requirements - Meets the needs of advanced wireless base stations (BTS) where systems need to offer high flexibility and allow dynamic resource utilization among a large number of cores - Delivers exceptional power efficiency, while maintaining software flexibility - Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market - Additional software components can be easily developed or licensed through CEVA s partners - Significantly accelerates multi-mode modem design

Applications

Wireless Cells Baseband Processing
  • Scalable from Pico and Metro Cells up to Macro Cells and Cloud RAN
  • Supporting: LTE-Advanced, HSPA+, TD-SCDMA, Wi-Fi 802.11ac, and more
Remote Radio Heads (RRH)
  • Targeting digital frontend processing
  • Handling advanced DSP functions including: Digital Predistortion (DPD), Up/down sampling Filters, Up/ down conversion, Quadrature Modulation Correction, DC Offset Corrector, Carrier Frequency Offset Corrector and more
Wireless Backhaul
  • Wideband spectrum point-2-point wireless communication supporting up to 4096 QAM
  • Targeting digital frontend processing
Enterprise Wi-Fi and WiFi-Cellular Offload
  • Addressing Wi-Fi 802.11ac AP and Small Cells use cases supporting 3x3, 4x4 MIMO delivering up to 1.7Gbps

Features

Highly powerful vector processor supporting fixed and floating point operations
  • Over 400 16-bit operations in a cycle
  • Floating point ISA offering over 40 GFLOPs
High performance architecture
  • 1.3GHz @ 28nm process
  • 64 16-bit fixed-point MACs
  • Variable 16/32-bit instructions
  • 12-Stage pipeline
Comprehensive multicore support
  • Fully featured data cache
  • HW support for cache coherency
  • System interconnect with automated management
  • Dynamic scheduling support
Optimal hardware-software partitioning via a mix of vector DSP and hardware accelerators Easy software development
  • Advanced IDE
  • Optimizing C compiler with Vec-C support (dedicated support for vector processors)
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • RTOS
  • Smooth migration path from off the-shelf ASSPs
  • MATLAB bi-directional connectivity (optional)
Open architecture and standardized APIs Complete set of optimized communication libraries including: LTE-Advanced, LTE, HSPA+, TD-SCDMA, Wi-Fi and more

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