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FlexNoC® AI Package complements FlexNoC interconnect IP, adding technologies for artificial intelligence (AI) and machine learning (ML) chip design.

The optional Arteris® FlexNoC® AI Package automatically generates mesh, ring and torus interconnect topologies. Unlike black box compiler approaches, SoC architects can edit generated topologies and also optimize each individual network router, if desired.


  • Highly efficient Multicast / Broadcast writes
  • VC-Link™ Virtual Channels
  • Source Synchronous Communications
  • Automatically generate ring, mesh, and torus networks
  • HBM2 and multichannel memory support
  • Meet ISO 26262 ASIL D requirements with optional Resilience Package
  • Automate timing closure assistance with optional PIANO Timing Closure Package

Block Diagram


  • Automated topology generation for mesh, ring and torus networks – FlexNoC 4 AI enables SoC architects to not only generate AI topologies automatically but also edit generated topologies to optimize each individual network router, if desired.
  • Multicast – FlexNoC 4 AI intelligent multicast optimizes the usage of on-chip and off-chip bandwidth by broadcasting data as close to network targets as possible. This allows for more efficient updates of DNN weights, image maps and other multicast data.
  • Source synchronous communications – Helps avoid clock tree synthesis, physical placement, and timing closure problems when spanning long distances on AI chips, which can be larger than 400 mm2.
  • VC-Link™ virtual channels – Allows sharing of long physical links in congested areas of the die while maintaining quality-of-service (QoS).
  • HBM2 and multichannel memory support – Ideal integration with HBM2 multichannel memory controllers with 8 or 16 channel interleaving.
  • Up to 2048-bit wide data support – With non-power of 2 data width and integrated rate adaptation

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