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High Throughput, Low Cost, Low Power

The InferX X1 Edge Inference Co-Processor is optimized for what the edge needs: large models and large models at batch=1. InferX X1 offers throughput close to data center boards that sell for thousands of dollars but does so at single digit watts and at a fraction of the price. InferX X1 is programmed using TensorFlow Lite and ONNX: a performance modeler is available now. InferX X1 is based on our nnMAX architecture integrating 4 tiles for 4K MACs and 8MB L2 SRAM. InferX X1 connects to a single x32 LPDDR4 DRAM. Four lanes PCIe Gen3 connect to the host processor; a GPIO link is available for hosts without PCIe. Two X1's can work together to double throughput.

Block Diagram


  • nnMAX Compiler supports Tensorflow Lite and ONNX
  • Numerics: INT 8x8, 16x8 run at full 1.067GHz
  • Numerics: BFloat 16x16 takes 2 cycles per MAC
  • BFloat16 accumulation is done at BF24 precision.
  • On Chip Hardware converts INT to BF and back
  • INT8/16 and BF16 can be mixed layer by layer
  • Winograd Transformation Hardware for INT8
  • Unique architecture based on inference optimized eFPGA
  • InferX uses an array of nnMAX MAC clusters with SRAM
  • Clusters of 64 nnMAX connected by patented XFLX/ArrayLinx nonblocking interconnects reconfigured each layer
  • SRAM bandwidth utilization is very high
  • Weights are loaded for the next layer in the background

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