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All Silicon IP

Overview

Through customized, targeted IP offered in 7nm FinFET technology and a modular design methodology, the neuASIC platform removes the restrictions imposed by changing AI algorithms. The platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators. With the use of a Design Profiler and AI Engine Explorer, eSilicon-developed and third-party IP can be configured as AI "tiles" via an ASIC Chassis Builder, allowing early power, performance and area (PPA) analysis of various candidate architectures. The neuASIC platform also uses a sophisticated knowledge base to ensure optimal PPA.

The elements of neuASIC IP library include functions that are found in most AI designs, resulting in a core architecture that is both optimized and durable with respect to AI algorithm changes. Specific algorithm modifications can be accommodated through a combination of minor chip revisions that integrate appropriate AI "tiles" or modifications of the 2.5D package to integrate appropriate memory components.

eSilicon-developed AI-targeted "tiles" include subsystems such as convolution engines that have MAC blocks tightly coupled with memory subsystems optimized for AI that result in lowest area and power. Special innovative structures have been developed for data transfer across memory subsystems. It also includes transpose memory, among others. The physical interface (PHY) to the HBM memory stack is also part of the library. Approximately 100 engineers at eSilicon are working on the design and silicon hardening of this AI IP.

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