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All Silicon IP

Overview

The D1088 is a 5-stage pipeline integer processor with integrated DSP offering 130 DSP SIMD (single instruction, multiple data) instructions. Targeting the real time processing requirements of power-constrained multimedia applications, At 90nm low power process, the D1088 delivers 588 DMIPS, 134 percent higher than the competing offerings. When measured with the popular Whetstone floating-point benchmark , the D1088 achieves 92 percent better performance. When running the popular and comprehensive (over 200) DSP libraries, the D1088 is 116 percent faster with half the code size. Even with the above advantages, D1088 still comes with a little smaller die area and power per MHz. The D1088’s optimized DSP libraries and C/C++ compiler make algorithm programming easier.

Tightly integrated Integer and DSP processor architectures are not new, but most were designed for applications where power was not as much a constraint as it is today. The new D1088 was designed with this new reality in mind. It contains functionality to enhance efficiency and reduce code size. For example, to significantly boost the computational performance in matrix, filtering, Fourier Transform, and statistics functions, it can execute 4-way 8-bit, or 2-way 16-bit SIMD instructions in a single latency as well as 8-bit and 16-bit SIMD instructions. In addition, for multimedia applications, the D1088 also supports 64-bit as add, subtract, and multiply mixed computation.

Benefits

AndeStar™ V3 Architecture
  • Better performance for modern compiler
  • Smaller code size
  • Efficient voice applications
  • Trade-off between core size and performance requirements
  • Faster SW development and easier maintenance
  • Efficiency and protection with a dedicated kernel stack pointer
  • More performance
  • Better program code size and performance
  • Quick identification of interrupt sources and fast assignment of service routines
  • Full range address space
  • Easy to program and friendly to compiler

CPU Core

  • Superior performance-per-MHz
  • Superior performance-efficiency, while allowing for high speeds
  • Better performance for branches
  • Stack size determination and runtime overflow error detection
  • Simplification SoC design and debugging
  • Program code performance tuning
  • Basic read/write/execute memory protection with minimum cost

Memory Subsystems

  • Higher performance for large program size
  • Higher efficiency for program execution
  • User-selectable bus interface for optimal efficiency

Applications

  • Video event data recorder (VEDR)
  • Wireless device
  • Networking device
  • Storage device
  • DSC
  • DVC
  • Digital home
  • Embedded controller
  • Block Diagram

    Features

    AndeStar V3 Architecture
    • 21st-century RISC instruction set
    • 16/32-bit mixable opcode format
    • Optional saturation instructions
    • 16 or 32 general-purpose registers
    • All-C Embedded Programming
    • Shadow stack pointer
    • Hardware divider
    • Aligned and unaligned load/store multiple word instructions and post-increment load/store memory accesses
    • Direct support of up to 32 interrupts with programmable priority levels
    • 4G address space
    • Memory mapped IO

    CPU Core

    • 2.41 DMIPS/MHz
    • 3.90 CoreMark/MHz
    • DSP extension instructions
      • > 130 instructions
      • Zero-overhead loop
      • Saturation and Rounding
      • Fractional Q31/Q15/ Q7 data types
      • Integer U32/U16/ U8 data types
      • 16-bit and 8-bit SIMD instructions
      • 64-bit signed/unsigned addition & subtraction
      • GCC intrinsic functions to use in C
      • GCC vector data type for SIMD instructions
    • Extensive branch predication (BTB and RAS)
    • Hardware stack protection
    • Processor state bus
    • Performance monitors
    • Extensive clock gating and logic gating
    • N:1 core/bus clock ratios
    • Low-latency vectored interrupt
    • Completion of most operations in 1 cycle
    • PowerBrake technology
    • Coprocessor interface

    Memory Subsystems

    • I & D Cache
      • Virtually Indexed and Physically Tagged (VIPT)
      • Size:4KB to 64KB, line size:16B/32B
      • Set associativity: Direct-mapped/ 2 Way
    • Optional External Instruction and Data Local Memory
      • Size: 1KB to 4MB
      • ILM: program code, data and IO
      • DLM: program data
    • Optional 2D local memory DMA
    • BIU supports 32-bit AHB/2AHB/AHB-lite/APB/AXI

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