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Overview

N15/N15F are dual-issue superscalar AndesCore™ processors capable of delivering performance at 5.41 CoreMark/MHz, the highest among the same level products in the industry. N15/N15F comes with a variety of configuration options, including MMU, cache and local memory. The 64-bit data buses for caches, local memory and the main bus provide the bandwidth needed for instruction fetch and data access. N15F includes a built-in IEEE-754 compliant floating point unit that enhances the floating point processing capability. N15/N15F is designed for diversified performance-driven applications on the embedded Linux, Real-Time OS or bare metal environment.
  • Dual-issue pipeline
  • Caches for fast code and data accesses
  • Local Memories for deterministic code and data accesses
  • Built-in IEEE754-compliant FPU coprocessor (N15F)
  • Memory Management Unit (MMU) for Linux
  • 64-bit AXI4/AHB/AHBx2 bus interface
  • Benefits

    AndeStar ™V3 Architecture
    • Better performance for modern compiler
    • Smaller code size
    • Trade-off between core size and performance requirements
    • Faster SW development and easier maintenance
    • Efficiency and protection with a dedicated kernel stack pointer
    • Better program code size and performance
    • More performance
    • Quick identification of interrupt sources and fast assignment of service routines
    • Full range address space
    • Easy to program and friendly to compiler

    CPU Core

    • Superior performance-per-MHz
    • Capable of processing two instructions in parallel to accelerate performance
    • Better performance for branches
    • Stack size determination and runtime overflow error detection
    • Simplification SoC design and debugging
    • Program code performance tuning
    • Basic read/write/execute memory protection with minimun cost
    • More performance
    • Lower power
    • Simplified SoC integration
    • Faster context switch for real-time applications
    • Better performance-efficiency
    • Peak power consumption reduction
    • Better power management efficiency
    • For floating point application

    Memory Subsystems

    • Higher performance for large program size
    • Higher efficiency for program execution
    • Code and data integrity protection
    • Efficient data transfer
    • User-selectable bus interface for optimal efficiency

    Applications

  • Industrial Automation
  • Advanced Motor Control
  • Advanced Driver Assistance System (ADAS)
  • Global Position System (GPS)
  • Unmanned Aerial Vehicle (UAV)
  • Sensor Device/Sensor Hub
  • Block Diagram

    Features

    AndeStar V3 Architecture

    • 21st-century RISC instruction set
    • 16/32-bit mixable opcode format
    • 32 general-purpose registers
    • All-C Embedded Programming
    • Shadow stack pointer
    • Radix-4 hardware divider
    • Aligned and unaligned load/store multiple word instructions and post-increment load/store memory accesses
    • 64-bit load/store unit
    • Direct support of up to 32 interrupts with programmable priority levels
    • 4G address space
    • Memory mapped IO

    CPU Core

    • 3.36 DMIPS/MHz
    • 5.41 CoreMark/MHz
    • 6-stage dual-issue pipeline
    • Extensive branch predication (BTB and RAS)
    • Hardware stack protection
    • Processor state bus
    • Performance monitors
    • Extensive clock gating and logic gating
    • N:1 core/bus clock ratios
    • Low-latency vectored interrupt
    • Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accesses
    • PowerBrake technology
    • QuickNap™ automatic state management for fast power-off and wakeup
    • Floating point unit (N15F)
      • IEEE 754 Compliant
      • Single precision (SP) or Double precision (DP)
      • 32 registers for SP, 16 or 32 registers for DP
      • Support all rounding modes and exceptions
      • Support Flush-To-Zero mode to speedup denormalized number processing

      Memory Subsystems

    • I & D Cache
      • Virtually Indexed and Physically Tagged (VIPT)
      • Size:4KB to 64KB, line size: 32B
      • Set associativity: 2-way (I-Cache), 4-way (D-Cache)
    • Optional External Instruction and Data Local Memory
      • 64-bit ILM: program code, data and IO
      • ILM: program code, data and IO
      • Dual 32-bit DLM: program data
    • ECC or Parity for soft-error protection (Parity protection is valid for D-Cache and DLM only)
    • Optional 1D/2D DMA with 64-bit transfer
    • BIU supports 64-bit AXI4/AHB/AHB2

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