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Overview

Provides an easy way to implement ARINC 818 compliant interfaces in Xilinx’s FPGAs. Avionics Digital Video Bus (ADVB) is a video interface and protocol standard developed for high bandwidth, low latency, uncompressed digital video transmission in avionics systems. The DO-254 ARINC 818 XGA Transceiver Core IP provides a serial transmitter interface which takes XGA video data as the input, and outputs the video data in Fibre Channel frames conforming to the ARINC 818 video specification. The DO-254 ARINC 818 XGA Transceiver IP Core also provides a serial receiver interface which takes Fibre Channel frames conforming to the ARINC 818 video specification.

Block Diagram

Features

  • Complete header/ancillary data recovery
  • Embedded ancillary data with real time update
  • Flexible video resolution/frame rates
  • Low Latency
  • Many pixel packing and input formats
  • Progressive and interlaced video
  • Receiver error and status detection
  • Simple pixel bus transmitter interface
  • Supports V5, V6 and S6
  • Supports line synchronous transmission
  • Supports link speeds up to 4.25 Gbps

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