Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Automotive, Avionics and High safety  > Avionics
Download Datasheet        Request More Info
All Silicon IP


The 1553-BC/RT/MT IP core implements a serial link controller enabling the development of Bus Controllers (BC), Remote Terminals (RT), and Monitor Terminals (MT) compliant with the Department of Defense MIL-STD-1553B standard.

Field-proven in many civilian and military avionics systems and optionally accompanied by a DO-254 certification package, the core is highly reliable and ready for aviation applications.

The core can operate as a Bus Controller, Remote Terminal, and Monitor Terminal at the same time. The BC and RT modules can also be disabled at run time, or at synthesis time to reduce silicon requirements. The Monitor Terminal provides 1553 Bus Monitor (BM) functions within the core. It is available under all configurations, and can be enabled or disabled at run time.

The 1553-BC/RT/MT is suitable for the implementation of MIL-STD-1553B Bus Controllers (BC), Remote Terminals (RT), and Bus Monitors (BM) in avionics systems.

The 1553-BC/RT/MT is designed to enable flexible message scheduling, monitoring, and filtering for all types of traffic in different bus architectures and with minimum overhead for the host processor. Messages are conveyed to/from the host via shared memory space organized in 16-bit words, and configure the core via its 16-bit wide register interface.


Compatibility with popular IC devices enables the core to work with industry-standard drivers and software applications. Special versions are available for drop-in replacement of legacy ICs.


The 1553-BC/RT/MT is suitable for the implementation of MIL-STD-1553B Bus Controllers (BC), Remote Terminals (RT), and Bus Monitors (BM) in avionics systems.

Block Diagram


MIL-STD-1553 Link Controller
  • BC/RT/MT; BC-only, RT-only and Multi-RT configurations
  • Supports dual-redundant buses
  • Supports flexible message scheduling and minimizes host processor load
    • Programmable auto-repeat retry-on-error, and stop-on-error modes
    • Programmable inter-message gap (4?s to 65.5ms)
  • Enables efficient message monitoring and filtering for all types of traffic
    • Up to 30 Rx and 30 Tx programmable sub-addresses
    • Single, Dual, and Circular data buffering modes
  • Error detection and status reporting for all transactions

Reliable and Proven

  • Deployed in many military and civilian avionic systems
  • Verified with numerous transceiver-transformer pairs.
  • Optionally delivered with DO-254 Certification Data Package
  • FMC FPGA board available for evaluation and/or in-field testing

Easy to Use

  • Compatible with industry-standard devices, enables use of existing software drivers and applications
  • Special versions available for replacement of legacy ICs

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.