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Overview

The A429-RxTx IP core is a multichannel transmitter (Tx) and receiver (Rx) compliant to the ARINC 429 standard.

Developed according to DO-254 ED-80 guidelines and field-proven in many civilian and military avionics systems, the core is highly reliable and ready for aviation applications.

The A429-RxTx core is designed to enable independent control of multiple receive and transmit channels with minimum overhead for the host processor. The number of Rx and Tx channels is configurable at synthesis time. Frames received or to be transmitted are stored in 32-bit wide FIFOs of synthesis-time configurable depth. The core provides access to the FIFOs and to its status and control registers via a generic 32-bit wide host interface.

Using the core?s control registers, the host can independently configure each of the channels. For each transmit or receive channel the data-rate (12.5 or 100 kbps) and parity generation or checking mode (odd or even) can be chosen. Receiving channels can also be programmed to filter data based on the label and/or the SDI fields of the incoming frames.

With frame filtering enabled, the core delivers to the host only the received messages that have specific label field values and SDI field values. Status information (FIFO occupancy, transmission or reception status, etc.), and possible reception errors are reported to the host via the core?s status registers, but also via a rich set of maskable interrupts.

Applications

The core is suitable for devices or systems with an ARINC 429 interface and designed for aviation applications such as flight guidance and navigation, or flight data communication and recording.

Block Diagram

Features

Multichannel ARINC 429 Rx/Tx
  • Any number of Rx and Tx channels (default is 16 each)
  • Programmable data rates for each channel: 12.5 or 100 kbps
  • Programmable parity generation (Tx) and checking (Rx): Odd or even
  • Flexible received frame filtering based on Label (up to 256 different labels) and/or Source/Destination Identifier (SDI) fields
  • Receiver detects and reports parity, label, and SDI errors
  • Independent, configurable-depth, 32-bit wide, Receiver and Transmitter FIFOs

Reliable and Proven

  • Developed according to DO-254 ED-80 (DAL-A) guidelines
  • Deployed in many military and civilian avionic systems
  • Verified with large number of driver and receiver modules
  • FMC FPGA board available for evaluation and in-field testing

Easy to Use

  • Extended flexibility defined by pre-synthesis parameters for:
    • input clock frequency
    • number of channel
    • FIFO depth and thresholds
  • Labels memory size
  • Loopback mode for self-testing
  • Supports standard line drivers and receivers.

Deliverables

  • Source-code VHDL RTL or targeted netlist
  • Testbench
  • Comprehensive documentation
  • Optional DO-254 Certification Data Packages .

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