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Gigacoms management and engineering team brings in 25+ years of experience in ASIC design services with many successful customer engagements and hundreds of successful tape outs. With the recent merger of NanoAsics, Gigacom brings in the capability to provide design services from Architecture design to GDS2. RTL Design/Verification

Our RTL Design/ verification team has developed and delivered several first pass siliconover the years. The team has a broad range of experience in HDL design, Verification (VMM, OVM, UVM), FPGA verification, silicon bring up and characterization. Test vector development with excellent debug skills.


Gigacoms physical Design team brings in 25+ years of experience in Silicon Valley, in put together CAD flows/ methodologies, building large off-shore Physical Design teams with critical leadership in Silicon Valley.

With the recent merger with nanoAsics, Gigacom offers a complete Physical Design solution for ASICS targeted up to 28nm (TSMC and Global Foundries) using Cadence/ Synopsys/ Mentor EDA tools.

Analog Design/Layout

As an extension of Gigacoms own Analog Design/ Layout team, Gigacom offers Analog Layout services built a strong track-record and customer base. A high level summary of Gigcoms analog Layout Design Capabilities is summarized

Projects executed

RTL Design/Verification

Sample Projects :

Aurora Link LayerRTL design of Link Layer interfacing with ARM HSSTP PHYVerification of Link Layer
PCIEControllers from Snowbush, PLDSnSys Verification IP

Sample Projects :

NetworkingTSMC 40nm G2 chips, > 200mm2 each, ~30 people in 5 locations, 667MHz main frequencyOwned all aspects of both chips, including methodology development, P&R for over 20 blocks, and sign-off closure
Low Power wirelessGlobalfoundries 40nm LP2 different chips with integrated PMU, AFE, multiple processors, and several high-speed interfaces, 340MHz main frequency, voltage and power-gated domainsOwned all PD, including methodology, and project management (nanoASICs, and customer resources) Provided resources for management, Top-level, block-level, STA, and DRC/LVS
EthernetTSMC 28nm G2 chips, 10G Ethernet, 667 Main frequency, > 150mm2 eachOwned top-level, methodology, timing sign-off, and DRC/LVS sign-off. Provided resources for top-level, block-level, STA, and DRC/LVS

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