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Overview

Synopsys DesignWare??aRT is a hardware module that can be integrated into any system-on-chip (SoC) within the DesignWare ARC configurable architecture. Delivered via the DesignWare ARChitect configuration tool as an IP library component, it enables rapid software debug with minimal increase in die size and no power consumption penalty. DesignWare SmaRT gives developers the ability to trace program execution precisely in the real system. They can therefore diagnose bugs that are difficult to reproduce in system simulators, or only become apparent when the system is run at full speed. The system works by recognizing any change of program flow control: the relevant source and destination instruction addresses are then recorded within a stack structure. When the processor is halted, the resultant execution history can be read back by the MetaWare??bugger via the SoC s JTAG port: no special interfaces or external hardware are required.

Features

  • Easy To Integrate: Using this GUI-based design tool allows DesignWare SmaRT to be configured for use within devices based on any DesignWare ARC core
  • Easy To Use: DesignWare SmaRT is designed for use in conjunction with the MetaWare Debugger. The debugger can be used to switch DesignWare SmaRT tracing on and off as part of normal program execution, by setting a control bit. Trace results can be displayed in an intuitive fashion, along with other program information available to the debugger

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