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All Silicon IP All Verification IP

Overview

Frustrated by all of the manual effort and time you're spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you'll be able to generate 10X more tests using this platform. In addition, with its integrated debugging capability, you'll be equipped to reproduce, find, and fix complex SoC-level bugs in order to improve the overall quality of your SoC.

Because it applies an appropriate level of abstraction, Perspec System Verifier can meet the growing challenges of validating SoC performance, function, and power, especially at advanced nodes. The platform is portable, supporting reuse across

  • SoC scope, from IP to the system level, including software
  • Platforms, including FPGAs, emulators, hardware description language (HDL) simulators, virtual platforms, and silicon
  • Generated tests can be run on all Cadence Verification Suite platforms, including XceliumTM Parallel Simulator, Palladium® Z1 Enterprise Emulation Platform, and ProtiumTM S1 FPGA-Based Prototyping Platform
  • Users, including architects, hardware developers, verification engineers, and software test engineers

Using Perspec System Verifier, you ll benefit from completeness of measurement, with coverage of functionality, flows, and dependencies. You ll also gain knowledge transfer advantages, since the formal, model-based system description supports knowledge sharing between different groups, particularly hardware and software engineers.

Benefits

  • Automation, which reduces manual effort and also provides complex tests that wouldn't be written manually
  • Abstraction and ease of use, specifying system-level scenarios in an intuitive, flexible GUI that doesn't require you to be an expert on the details of the system
  • Platform support, with a reuse model and tests that work across pre-silicon and post-silicon platforms

Block Diagram

Features

  • Goal-directed and true constraint solving
  • Multi-platform, multi-language solution leveraging existing standards and proven techniques
  • Coverage and automatic filling capabilities
  • Debug and coverage logging built into the generated C tests to speed both debug and analysis of coverage results

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