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Overview

The DesignWare long Term Evolution (LTE) Security Protocol Accelerator is a proven, high-performance security engine targeted at 3G and 4G wireless broadband 3GPP/LTE/LTE-Advanced technologies. The configurable DesignWare LTE Security Protocol Accelerator can be tailored to address the complex security requirements of mobile networks, platforms and devices, while minimizing costs. The wireless broadband market is expanding at an incredible rate. Mobile networks and platforms must support the explosion of wireless devices and applications, and bring all mobility benefits to a huge group of end users. New technologies like 4G LTE-Advanced (Release 10 and beyond) are being developed to address these challenges. 3G LTE technologies governed by 3rd Generation Partnership Project (3GPP) specifications defined in Releases 7, 8 and 9 are also still applicable to global mobile phone systems and networks. The DesignWare LTE Security Protocol Accelerator allows designers to adapt their products to address the complex security requirements of the latest mobile networks, platforms and devices. The security engine reduces the bus traffic and offers increased throughput by supporting efficient data sequencing as well as parallel processing of cryptographic operations (authentication and encryption/decryption). The accelerator framework includes an efficient programmable sequencer, Secure DMA engine, and cryptographic/hashing resources required for the computationally intensive confidentiality and authentication security algorithms specified in the 3GPP/ LTE/LTE-A standard.

Features

  • Highly configurable security accelerator
  • Supports AES, SNOW 3G, ZUC and KASUMI based crypto algorithms
    • Cipher algorithms: AES, KASUMI, SNOW 3G, ZUC
    • Cipher modes: CTR, f8, UEA1, UEA2, 128-EEA1, 128-EEA2, 128-EEA3
    • Hash/MAC algorithms: AES-CMAC, f9, UIA1, UIA2, 128-EIA1, 128-EIA2, 128-EIA3
    • Other modes: GSM A5/3, ECSD A5/3 and GEA3 keystream generation
  • Built-in scatter/gather DMA capability offloads system CPU
  • Optimal bus utilization
  • Increased throughput with combined hash and cipher operations
  • Secure bus option for systems which differentiate between secure and normal processing modes
    • ARM TrustZone Support
  • IV import feature - permits DMA of IV with associated payload
  • Reduced system processor loading with programmable interrupt coalescence
  • Dual-clock domain capability to run interface and crypto content in different clock domains
  • Support for big- or little-endian
  • Configurable 32- or 64-bit bus interfaces
    • AMBA AXI4
    • Low-Power
    • AMBA AHB
  • Optional virtualization allows sharing between multiple CPUs
  • Optional QoS capability allows multiple command priority queues for enhanced traffic management capabilities

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