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Overview

The Arm CoreLink CMN-600 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points.

The CMN600 model uses the baseline NoC library shipped with VisualSim Architect. This library models the routing, unique crossbar for each type of traffic- Request, Response, Data, and Snoop. There is a virtual channel support on the Egress port. All the standard Request Nodes, Slave Nodes, Bridges and Home Nodes are supported. The Snooping protocol is implemented and the XP can connect to AXI buses, Memory controllers and other Slaves. The base model demonstrates the implementation of a NoCon a semiconductor. Traffic originates at a NoC_TG block and traverses the network to arrive at a destination. The Source and Destination are set at the TG block. The link configuration is set in a Lookup Table. The Routers are connected to each other in a mesh pattern. Router is a called XP or CrossPoint. The Router support two devices per node and four network connections. The flows are based on message type and Quality of Service.

Applications

CMN-600 includes end-to-end QoS capabilities which support latency and bandwidth requirements for different types of devices. The QoS device classes are:
  • Devices with bounded latency requirements: These are primarily real-time or isochronous devices that require some or all of theirtransactions to be complete within a specific time period to meet overall system requirements.These devices are typically highly latency-tolerant within the bounds of their maximum latencyrequirement. Examples of this class of device include networking I/O devices and displaydevices.
  • Latency-sensitive devices: These are devices whose performance is highly impacted by the response latency incurred by their transactions. Processors are traditionally highly latency-sensitive devices, although a processor can also be a bandwidth-sensitive device depending on its workload.
  • Bandwidth-sensitive devices: These are devices that have a minimum bandwidth requirement to meet system requirements. An example of this class of device is a video codec engine, which requires a minimum bandwidth to sustain real-time video encode and decode throughput.
  • Bandwidth-hungry devices: These are devices that have significant bandwidth requirements and can use as much system bandwidth as is made available, to the limits of the system. These devices determine the overall scalability limits of a system, with the devices and system scaling until all available bandwidth is consumed.

Block Diagram

Features

  • Support Interconnect as a series of AHB/AXI buses and a Network-on-Chip
  • Support for RN-F, RN-I, HN-F, HN-I and SH-F
  • Support two devices per node and 4 network interfaces for CMN600
  • Support bridges and DMA interfaces
  • Supports up to 8 memory controllers
  • Supports cache coherency using the Snoop messages for shared memory addresses
Protocol
  • ARM CMN-600
  • Corelink NiC400
  • Corelink NiC550
  • Model Link

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