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Higher signal voltage ratings, Low power, High robustness, High speed/RF


Several interfaces have distinctive signal conditions (5V or even 20V), for instance for battery connection (4.5V-5V battery), legacy interface communication, or USB.
Sofics engineers built 5V and beyond tolerant ESD protection clamps in CMOS from 180nm to 12nm using the standard process.

The reduction of leakage in functional circuits is paramount. Sofics has a specialized set of solution with extremely low standby power.

Sometimes 1 or 2 kV HBM is not enough: some PHY s or IC need higher ESD protection ratings. Some even require system-level ESD protection on-chip! Any ESD performance is possbile in all process nodes - ask us!

To get the most out of the process technology, the I/O s must support the highest frequencies. To achieve this, Sofics proposes a twofold method:

  • Allow thin gate devices in the I/O
  • Reduce parasitic capacitance

Block Diagram


  • Non-standard signal voltages
  • Low power requirement
  • High Robustness
  • Low capacitance for high speed/frequency

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