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MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin counts combined with excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides a silicon-proven and low-power M-PHY in different process nodes. The M-PHY IP follows MIPI M-PHY v3.1 spec and supports full range of high-speed (HS) and low-speed (LS) data transfer. It is compliant to the RMMI interface which allows a seamless integrations with upside UNIPRO controllers. The M-PHY IP is designed for wide Type-I applications and is optimized for UFS (Universal Flash Storage). It not only supports a very short sync length for TX/RX sync length but also supports a unique reference-less mode during LS operation. Meanwhile, M31 also provides various lane configurations for the M-PHY IP to meet different requirements of transmitter and receiver bandwidth.

Block Diagram

Tech Specs

Maturity Silicon proven


  • Supports RMMI interface for Type-I applications like UNIPRO protocol (UFS,CSI-3, DSI-2), and LLI
  • High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B, with scalable power consumptions
  • Provides hibernate or supper-hibernate mode to meet mobile device requirement
  • Burst mode CDR with short sync length ( < 16SI )
  • Low speed PWM Gears from G1 to G5 with ultra-low power consumptions
  • Supports reference-less function during low-speed operation
  • Common lane configuration facilitates the lane scalability
  • Low latencies to switch to/from different power states
  • Supports multiple signal amplitudes
  • Supports strong BIST functions to ease the mass production tests

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