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Advanced graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the increasing compute performance brought by advanced process technologies. With the DesignWare HBM2 IP solution, designers can achieve their memory throughput requirements with minimal power consumption and low latency. The complete DesignWare HBM2 IP solutions include controller, PHY and verification IP, enabling designers to achieve up to 307 GB/s aggregate bandwidth, which is 12 times the bandwidth of a 72-bit DDR4 interface operating at 3200 MB/s. In addition, the DesignWare HBM2 IP solution delivers approximately 10X better energy efficiency than DDR4. The DesignWare HBM2 IP solution leverages elements from Synopsys silicon-proven DDR4 IP, which has been validated in hundreds of designs and shipped in millions of systems-on-chips (SoCs), enabling designers to lower integration risk and accelerate adoption of the new standard. The DesignWare HBM2 PHY (Figure 1) is provided as a set of hard macrocells delivered as GDSII. These hard macrocells include integrated application-specific HBM2 I/Os required for HBM2 signaling and are easily assembled into a complete 512- or 1,024-bit HBM2 PHY. The design is optimized for high performance, low latency, low area, low power, and ease of integration.

Block Diagram


  • Complete HBM2 IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
  • DesignWare IP implementation supports data rates up to 2400 Mb/s, which is 20 percent faster than the HBM2 JEDEC standard specification
  • Pseudo-channel mode doubles the number of channels, resulting in smaller fetch size and higher performance
  • The HBM2 IP is based on Synopsys silicon-proven HBM and DDR4 IP that has been integrated into hundreds of SoC designs
  • Supports 2.5D-based JEDEC standard HBM2 SDRAMs with data rates up to 2400 Mbps
  • DFI 4.0-compatible interface
  • PHY independent training capability
  • Comprehensive set of design-for-test (DFT) features

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