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All Silicon IP All Verification IP


The Synopsys DesignWare® HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based applications. The silicon-proven HDMI 2.1 IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports the required features of HDMI 2.1 including dynamic HDR and enhanced audio return channel (eARC) and more, ensuring higher video quality and most advanced audio formats.

The complete power- and area-optimized HDMI 2.1 RX IP solution encompasses a suite of configurable digital controllers, high-speed, mixed-signal PHYs, PLL, verification IP, High-Bandwidth Digital Content Protection (HDCP) IP, IP Prototyping Kits, Linux software drivers, and IP subsystems. Having all necessary design blocks for the HDMI subsystem enables system-on-chip (SoC) designers to lower integration risk and accelerate time-to-market.


  • HDMI 2.1 RX IP solution includes PHYs, controllers, verification IP
  • Compliant with the HDMI 2.1, 2.0, 1.4 and HDCP 2.2, 1.4 specifications
  • Support for key HDMI 2.1 features such as fixed-rate link capable of 48Gbps aggregate bandwidth, enhanced metadata packets including dynamic HDR, eARC, auto low-latency mode and variable refresh rate
  • Optimized for low power and small area

Tech Specs

Geometry nm16
Maturity Available On Request
Target Process NodeTSMC 16nm FFC


  • Timing hardened blocks simplify placement and design closure
  • Configurable controller architecture optimized for power, performance, and area


  • Databook
  • Application notes, Assembly guidelines
  • Simulation model
  • Testbench
  • Design files kit: Behavioral model, LEF file & .LIB file, GDSII layout database

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