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VISENGI s H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. VISENGI offers two encoder variants to meet the different targets of features, resource usage, and compression:

  • H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: the IP core is larger but offers a significantly better compression
  • H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes): the IP core is smaller but yields less compression. It does not require external memory.

Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle.

Achieves UltraHD on mid-range and low-cost Spartan-6/Cyclone III FPGAs. 4K 60 on Artix-7 and Cyclone V. 8K30 on Arria 10 and Zynq 7030.

Block Diagram


  • Video compression standard ITU.T Rec. H.264 | ISO/IEC 14496-10 AVC.
  • EXTREME SPEED, providing a constant throughput of 5.2 pixels encoded per clock cycle.
  • Achieves 8K30 on mid-range Zynq-7030 and Arria 10 FPGAs
  • Achieves UltraHD 4K on low-end and low-cost Spartan/Cyclone FPGAs
  • Realtime configurable VBR/CBR mode (Variable/Constant Bit Rate) automatically controls all H.264 parameters.
  • Very low latency (just 16 lines time).
  • High 4:4:4 Predictive Profile (H264E-P) and CAVLC 4:4:4 Intra Profile (H264E-I and H264E-P).
  • Highest level (5.2) of resolutions and frames per second allowed by H.264 standard attained at just 102 MHz (most low-range FPGAs).
  • Preserves full color fidelity with color subsampling 4:4:4.
  • Selectable number of predicted frames (P) per keyframe (I) on H264E-P.
  • Output in Byte stream format (raw .264) for easier encapsulation.
  • (H264E-P) Full reconstructed video preview output.
  • (H264E-I) Optional pseudo-reconstructed video preview output.
  • Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output.
  • Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.
  • Optional AXI4-Stream Pixel-Input and Encoded-Output interfaces.
  • Optional optimized pixel input mode to boost shared memory efficiency.


  • Technical support via email
  • IP Core Datasheet
  • Xilinx Vivado drag n drop instance
  • Altera Qsys drag n drop instance
  • Linux driver for embedded setups
  • Example SW control application

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