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The Atria Logic AL-H264D-HW is a hardware-based, low power, low latency, feature-rich, H.264 (AVC) Baseline Profile video decoder IP core, targeted for mobile and non-mobile, low power devices in industrial, medical and CE applications. Industrial applications include remote monitoring of manufacturing plants, remote control of UAVs, and digital signage for advertising and information displays in hotels, ATMs, gas pumps, kiosks, etc. Medical applications include endoscopic, assisted surgery and remote diagnostics applications, CE applications include in-flight and automotive infotainment systems, netbooks, tablets and smartphones.

The decoder supports Baseline Profile I+P decoding up to Level 4.1 (1080p30), as well as error resiliency/robustness with Arbitrary Slice Ordering (ASO), Flexible Macroblock Ordering (FMO) and skipped macroblock support when receiving video data packets over unpredictable networks.


  • Fully ISO/IEC 14496-10 standards compliant
  • Speed and power-optimized ME engine
  • Fully software-optimized implementation
  • Support for broad range of ARM processors
  • Low-power optimized implementation


  • Remote monitoring
  • UAV control
  • Digital signage
  • Endoscopy
  • Assisted surgery
  • Remote diagnostics
  • In-flight and in-car infotainment
  • Netbooks, Tablets & Smartphones

Block Diagram


  • H.264 I+P Baseline Profile decoding
  • Support for all resolutions, frame rates and bit rates up to Level 4.2
  • Up to SVGA (800x600) support on FPGAs
  • Up to 1920x1080p60 support on ASICs
  • Multi-stream decode scalability
  • ASO, FMO and skipped macroblock support for error resiliency and robustness
  • Horizontal motion vector range of +/-2048
  • Vertical motion vector range of +/- 512
  • 1/2 and 1/4 pel motion compensation
  • Support for all 4x4 and 16x16 luma and all chroma modes
  • Up to 16 motion vectors per macroblock
  • Support for cross-frame boundary motion vectors
  • In-loop Deblocking filter
  • Very low latency at ~0.3sec
  • Synchronous, positive-edge clocking scheme
  • Low power modes via clock-gated, multi-clock domains
  • Register-level configuration and control over AMBA/AVALON bus
  • RTL implementation
  • ASIC and FPGA implementation support

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