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Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1. High speed processing with low clock frequency.Suitable for digital still camera,facsimile and surveillance camera systems.


  • Compact and low power consumption by DMNA
  • Speed Variations such as 1,4,8 pixels/clock
  • High performance - Full HD x 120 pictures per second at 63 MHz operation clock(4pixels/clock)
  • Wide range of picture size - 8x8 to 65528x65528 pixels
  • Flexible customization of interface specification to make easy to connect with various devices
  • Easy to port for FPGA
  • Features

    • Input/Output Format - YUV 4:4:4/4:2:2/4:2:0/4:0:0
    • Input data bus width - 32bits (1 pixel/clock), 64bits (4 pixel/clock)
    • Output data bus width - 32bit (1 pixel/clock), 64bits (4 pixel/clock)
    • CPU bus width - 32bits
    • Error detection during decoding illegal stream

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