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The Trilinear Technologies M11 digital video decoder core provides standards compliant DV decoding using a high-performance and low gate count implementation. The fully synchronous core decodes 25Mbps, 50Mbs, and 100Mps DV streams recorded at either 50Hz or 60Hz. Using a complete hardware implementation, the M11 core is capable of operating with low CPU overhead while providing the highest quality results.

Block Diagram


  • Decodes all DV bit rates and formats
  • Low CPU overhead
  • Memory interface tolerant of high latencies ideal in a shared memory architecture
  • Fully synchronous soft-core
  • Comprehensive support plan
  • Complete HW / SW verification suite Core Details
    • IEEE-1180 Compliant IDCT Engine
    • Fully Synchronous Design
    • AMBA 2.0 APB Target Command and Control Bus Interface
    • 128-bit Memory DMA for maximum decode performance
    • 256MB addressable memory range
    • Source code fully portable between FPGA and ASIC with no modifications
    • Decoding core operating frequency from 75MHz (SD) to 133MHz (HD)

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