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The Display Stream Compression (DSC) standard from the Video Electronics Standards Association (VESA) offers visually lossless compression for high definition (HD) video in broadcast, automotive, medical and consumer electronics applications. The Trilinear Technologies M25 DSC 1.2 Decoder offers real time decompression of HD streams with resolutions from 480p up to 8K. The decoder core is fully compliant with the VESA DSC 1.2 standard and is available for both FPGA and ASIC platforms.The M25 core is delivered with an industry standard AMBA 3.0 Peripheral Bus interface for host configuration and decoder control. The encoded input interface is AXI4-Stream Protocol compliant and the output interface uses a streaming data structure with associated line and frame formatting signals. The DSC 1.2 Decoder core supports 8, 10, 12, 14 or 16 bits per pixel using either the RGB or YCbCr in 4:4:4 or 4:2:2 format.


  • VESA DSC 1.2 Compliant
  • Capable of decoding 4K video at 30fps in FPGA and ASIC
  • Decode 8K video at 30fps in ASIC applications
  • Low gate count implementation
  • Low latency implementation
  • Block Diagram


    • RGB or YCbCr encoded input
    • 8, 10 or 12 bits per color
    • 4:2:0 and 4:2:2 support
    • AXI 4 Stream Input Interface
    • AMBA 3.0 APB Host Interface


    Trilinear Technologies delivers an extensive design database for the M25 core. The database includes all of the files required to implement the design on multiple platforms including FPGA and ASIC technologies. In addition to the core implementation files, reference software drivers and applications are included along with the associated documentation to reduce the amount of time for software development.
  • HDL source files for the function design
  • HDL source files for block level and top level testing
  • Functional specification
  • Timing constraints summary document
  • Generic SRAM simulation models
  • C Reference Driver
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