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The Trilinear Technologies M27 DSC 1.2 Encoder offers real time compression of high definition streams with resoltions up to 8K. The Display Stream Compression (DSC) standard from the Video Electronics Standards Assocaiton (VESA) offers visually lossless compression for high definition applications. The M27 Encoder core is fully compliant with the VESA DSC 1.2 standard and is available for both FPGA and ASIC implementations. The M27 Encoder core is delivered with an industry standard AMBA 3.0 Peripheral Bus interface for host configuration and control. Input video is provided to the encoder using an industry standard parallel data format with line and frame indicator signals. The output interface is AXI4-Stream Protocol compliant. The Encoder core supports 8, 10 or 12 bits per pixel using either the RGB or YCbCr in 4:4:4 or 4:2:2 format.


  • VESA DSC 1.2 Compliant
  • Capable of encoding up to 4K video at 30fps in FPGA and ASIC
  • 8K compression available for select applications
  • Low gate count implementation
  • Low latency implementation
  • Block Diagram


    • RGB or YCbCr streaming input
    • 8, 10 or 12 bits per color
    • 4:2:2 and 4:2:0 support
    • AXI 4 Stream Output Interface
    • AMBA 3.0 APB Host Interface


    Trilinear Technologies delivers an extensive design database for the M27 core. The database includes all of the files required to implement the design on multiple platforms including FPGA and ASIC technologies. In addition to the core implementation files, reference software drivers and applications are included along with the associated documentation to reduce the amount of time for software development.
  • HDL source files for the function design
  • HDL source files for block level and top level testing
  • Functional specification
  • Timing constraints summary document
  • Generic SRAM simulation models
  • C Reference Driver
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