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The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm. The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution. Simple, fully synchronous design with low gate count.


  • HDTV suport
  • Low gate count
  • Multi-channel support
  • Progressive and interlaced video support
  • No external CPU required


  • Digital video recorders
  • Video wireless devices
  • Video surveillance systems
  • Hand held HDTV video cameras

Tech Specs

Market SegmentMultimedia


  • Fully compatible with the output of the OL_H264MCE encoder core
  • Up to Profile level 4.1 can be decoded
  • Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive)
  • Very low operational frequency : from ~1.5 MHz for QCIF @ 15 fps to ~250 MHz for 1920x1080 @ 30 fps
  • Direct support for both progressive and interlaced video
  • Single core HDTV support in FPGA : 720p (1280x720) at 30 fps in high end FPGAs (Virtex4) . 4 CIF (704x576) at 30 fps in low end FPGAs
  • No CPU required for decoding
  • Very low latency decoding

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